VHDL

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VHDL
2
Introduction

• ?????????,???????????,????????????,??????gate-leve
  l????????,?????????????????????
• ?????????????
• ????????,?????????????????
• Very High Speed ICs Hardware Description Language
  (VHDL)

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VHDL??????
4
VHDL??????
5
VHDL??????

• VHDL???(.vhd)
• -- VHDL Design Unit ????
• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY e-name IS
• --port declaration
• PORT (
• P-name mode type
• )
• END ENTITY e-name

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VHDL??????

• ARCHITECTURE a-name OF e-name IS
• --component declration
• COMPONENT .. END COMPONENT..
• --signal declaration
• SIGNAL s-name type
• BEGIN
• --Concurrent statements (????)
• END ARCHITECTURE a-name

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VHDL????

• library IEEE
• use IEEE.STD_LOGIC_1164.ALL
• entity IC7400 is
• Port ( a1,a2,b1,b2,c1,c2,d1,d2 in
  std_logic
• ao out std_logic
• bo out std_logic
• co out std_logic
• do out std_logic)
• end IC7400
• architecture a of IC7400 is
• begin
• ao lt not (a1 and a2)
• bo lt not (b1 and b2)
• co lt not (c1 and c2)
• do lt not (d1 and d2)
• end a

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Library ??????????

• 1?LIBRARY
• ??user???????????
• (library) IEEE
• ???, Simulator??Library????????? ,
• ?? .ini ??
• ????? ???????(??)?library?
• ????? ???????

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USE ?? library??package

• 2?USE
• ???library??package,??????????
• ???
• ?Package ?????????VHDL?
• ?????? (Objects)
• ?????TYPE,Sub-program(Function, Procedure),
• CONSTANT, Deferred constant?
  
• ????
• USE Lib-name .package-name.all.

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USE -------

• Compile?, ?????package??
• (1) ???library package
• (2) ???library package?
• Library?Use?????????Design unit (Entity)

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ENTITY ???? (DESIGN unit) ??

• ??(DESIGN)??
• Design- unit name ? external?? (ports)
• ???????(name pins)

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?? (Comment)

• hyphen -- ??,?? Carriage-return ???
• ????
• ?VHDL design ????????header
• ?? design unit, file name, function,
  modules Called,
• limitation, author ,
  revision number and date?
• ??
• -- Design unit y_func
• -- File name y_func.vhd
• -- Function Y(a,b,c)S(1,3,6,7)(not A and
  C) or (A and B)
• -- limitation No
• -- Author MS-Shiau
• -- Department of Electronics
  ,Feng-Chia University
• -- Revision V.1 12/31/2001

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PORT (?)

• ??? ..
• IC pins ,
• system external interface signals
• ??
• PORT(
• p1-name mode type
• p2-name mode type
• pN-name mode type )

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PORT ---- mode

• IN , OUT , INOUT , BUFFER
• IN ???????????
• OUT ?multi-driven , ?? feed-in (??????????).
• BUFFER (?OUT?,??feed-in?? ?????,?????)
• INOUT??PORTs??????????????

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Architecture

• 1?ARCHITECTURE
• ? Design-unit???? ????
• ????
• ARCHITECTURE a-name OF e-name IS
• SIGNAL s-name type -----
  declaration
• BEGIN
• Concurrent Statements (????)
• END Architecture a-name

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????(Description styles)

• 1????????(Description styles)
• (1)Structural ????????Netlist ??
• (??Component.VHDL? , ?Design-unit?
  Component ??, Component ??instantiation)
• (2)Behavior Process ??, Function or
  Procedure??
• (?? Sequential (timing????) statements)
• (3)Data-flow Boolean ???concurrent signal
  assignments
• (??data??,??,??????, ?Boolean???????)

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Description styles??
???? ?????
Structure style ?????????(Top-level)?design-module????Reuse???
Behavior style ?????????,??????????????
Data-flow style ?????????,????????????????
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DATA TYPE
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????

• VHDL????????????????????????
• ????
• ?? ?????? ???? ???
• ??? (Initial value)
• All signals have an initial value when
  simulation begins.
• ?User defined in the declaration (Ex
  0 )
• ?Default the 1st (left) value that
  appeared
• in type declaration
• ?Initial value assignment is ignored in H/W
  synthesis.
• ?Way for synthesis Global (Power-on )
  reset

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????

• ??(Class)
• (1)port, Signal
• ? Circuit-connection (Wire??or?????)
• ? Driver is scheduled by queue ie. Means
  they have time-delay)
• (2)Constant
• ?????????identifier ??????????.
• ??????????????
• (3)Variable
• ????process or??????.
• ??????wire or ??, Local-storage operation
• ?????????????
• (Updated immediately, no delay)
• (4)??(File)
• ??????????,??????????????

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??

• ??
• TYPE ???? IS
• ??(Default)
• ?Standard package ?IEEE package????????
• ??(User)
• ?User package ? or
• VHDL design unit??Architecture?Begin ?????

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?????Types??( STANDARD )

• Package STANDARD
• Type Boolean is (false,true)
• Type Bit is (0,1)
• Type Character is ( A,..,0,? )
• Type severity_level is (note, warning, error,
  fail)
• Type integer is range -2147483648 to
  2147483647
• Type real is range -1.7014110e38 to
  1.7014110e38
• Type time is range -9223372036854775807 to
  9223372036854775807
• Units fs Ps 1000 fs ns
  1000 ps us 1000 ns ms 1000 us
• sec 1000 ms min
  60 s hr 60 min End units
• Subtype natural is integer range 0 to
  integerhigh
• Subtype Positive is integer range 1 to
  integerhigh
• Type string is array (positive range ltgt) of
  character
• Type bit_vector is array (natural range ltgt)
  of bit
• Function now return time

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?????Types?? ( std_logic_1164 )

• Type std_ulogic is (U,X, 0,1, Z,W,
  L,H,- )
• Function resolved (s std_ulogic_vector)
  return std_ulogic
• Subtype std_logic is resolved std_ulogic
• Type std_ulogic_vector is array (natural range
  ltgt)of std_ulogic
• Type std_logic_vector is array (natural
  range ltgt)of std_logic
• Function and
• ----- Include and, nand , or, nor ,
  xor, not .
• ----- Conversion Function
• Function to_Bit to_Bitvector ,
  
• to_stdulogic
  to_stdulogicvector
• to_stdlogicvector

????
????
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?????Types??( std_logic_arith )

• 1992 Synopsys inc.
• Type Unsigned is array (natural range ltgt ) of
  std_logic
• Type Signed is array (natural range ltgt) of
  std_logic
• Functions
• (1)arithmetics , -, ,
• (2)Relation lt, gt, , gt, lt, /,
• (3)shift SHL (arg,count) , SHR (arg,count),
• Conversion Function
• CONV_integer
• CONV_SIGNED(arg,size) CONV_UNSIGNED
• CONV_std_logic_vector(arg,size)
• Note std_?signed/unsigned?? type Cast
  conversion
• BltUnsigned(A) Signed (A) ----- A
  std_logic
• Altstd_logic_vector(B) ----- B Signed
  or unsigned

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???(scale) --- Integer

• 1?Integer(default-defined)
• TYPE integer IS range ____________
  
• ? 32- ?? , ?? -(231) (231-1)
• ?????????????????????Size
• ??User-defined integer (range spec. use
  integer)
• TYPE my_integer IS RANGE range_low TO
  range_hi
• TYPE my_integer IS RANGE range_hi DOWNTO
  range_low
• TYPE my_integer IS RANGE ltgt
• Note ltgt --???(unconstrained)
  (???????)

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???(scale) --- Real

• 2?Real (range spec. use real)
• TYPE real IS range
• ???????? -1.0 e38 1.01e38
• ??
• Signal A real
• Alt 2.5E-15

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???(scale) --- Physical Type

• Physical Data Type

TYPE time IS Range ltgt --???????? Units
fs --???? ps1000
fs --???? ns1000 ps
us1000 ns ms1000 us
sec1000 ms min60 sec
hr 60 min END units
TYPE distance IS Range 0 TO 231-1
Units nm um1000 nm
mm1000 um cm10 mm
m1000 mm Km1000 m
END units
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???(Array)????

• ???(Array) ?? ??
• ?????????????????????????

• ??
• TYPE ary_name IS ARRAY (????) OF ????
• ??????,
• ???? ? To ? ?DOWNTO ? Integer lt gt
  ..unconstrained array
• Note Standard unconstrained array ?
  Bit_vector ? String
• TYPE ary_name IS ARRAY(d_1_range , ,
  d_n_range) OF ????
• Note ???? ????/?
• ???????ary_name (integer)

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???(Array)????

• ??? VHDL STANDARD package ?
• Bit_vector . Bit?????
• TYPE bit_vector IS ARRAY (natural ltgt) OF
  bit
• ??? ????????
• TYPE byte IS ARRAY (7 downto 0) OF bit
• TYPE word IS ARRAY (31 downto 0) OF bit
• TYPE Memory_name IS ARRAY (0 to 4096) OF
  word

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???(Array)????

• ?? ???????? ROM_ LUT
• -- ??ROM_look-up-table?????( 8X4 ???)
• TYPE Rom_block IS ARRAY (0 TO 7, 0 TO 3) OF BIT
  
• -- ????ROM_LUT? ??????
• CONSTANT ROM_LUT Rom_block (
• ( 0, 1, 1, 0 ),
• ( 0, 1, 1, 0 ),
• ( 0, 1, 0, 1 ),
• ( 0, 0, 0, 0 ),
• ( 0, 1, 1, 0 ),
• ( 1, 0, 1, 0 ),
• ( 0, 1, 1, 0 ),
• ( 1, 1, 1, 1 ) )

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???(Array)????

• 2-Dimension Array type declaration

???????? ????? 12?32 ?ROM???Type
?Method-1?1-D of 1D TYPE word IS ARRAY(31
downto 0) of bit TYPE ROM_TABLE IS ARRAY(11
downto 0) of word
?Method-2?2D-directly TYPE ROM_TABLE IS
ARRAY(11 downto 0 , 31 downto 0) of bit
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OPERATOR
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??
??(Logic) AND OR NAND NOR NOT XOR XNOR
??(Relation) / lt lt gt gt
??(????) - / MOD REM
?? -
?? ABS
??/?? SLL SRL SLA SRA ROL ROR
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??????
? ? ABS NOT
? ? / MOD REM
? ? SIGN SIGN ?
? ? ADD ADD ?
? ? / lt lt gt gt
? ? AND OR NAND NOR XOR XNOR
?????????????
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? ? ? ?

• ????? AND, NAND, OR, NOR, NOT, XOR, XNOR
• ?????NOT?????,????????
• ??????????????
• ?IEEE Library????????????????

?Example? -- truth table for "and" function
CONSTANT and_table stdlogic_table ( --
-----------------------------------------------
----- -- U X 0 1 Z W
L H - --
--------------------------------------------------
-- ( 'U', 'U', '0', 'U', 'U', 'U',
'0', 'U', 'U' ), -- U ( 'U',
'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), --
X ( '0', '0', '0', '0', '0', '0',
'0', '0', '0' ), -- 0 ( 'U',
'X', '0', '1', 'X', 'X', '0', '1', 'X' ), --
1 ( 'U', 'X', '0', 'X', 'X', 'X',
'0', 'X', 'X' ), -- Z ( 'U',
'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), --
W ( '0', '0', '0', '0', '0', '0',
'0', '0', '0' ), -- L ( 'U',
'X', '0', '1', 'X', 'X', '0', '1', 'X' ), --
H ( 'U', 'X', '0', 'X', 'X', 'X',
'0', 'X', 'X' ) -- - ) FUNCTION
"and" ( l std_ulogic r std_ulogic ) RETURN
UX01 IS BEGIN RETURN (and_table(l,
r)) END "and"
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?????

• Scalar object ?????? Overload function
• ????? Boolean ?(True/False)
• FUNCTION gt (L operand_type R operand_
  type ) RETURN BOOLEAN
• (Standard ?IEEE.std_logic_1164 package????)
• ??? USE IEEE.NUMERIC_STD

L(R) operand_type R(L) operand_type
IEEE-1076.3 Numeric_bit Numeric_std IEEE-1076.3 Numeric_bit Numeric_std
Signed Signed
Unsigned Unsigned
Signed Integer
Unsigned Natural
SYNOPSYS Std_logic_signed Std_logic_unsigned SYNOPSYS Std_logic_signed Std_logic_unsigned
Std_logic_vector Std_logic_vector
Std_logic_vector Integer
????integer, Signed ?Unsigned?? A
std_logic_vector SIGNED(A)
???Std_logic????
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?????

• ????
• 1?Integer ??
• ? ??MSB????
• ? ??MSB????, ??Signed extension??
• (1)?? Signed(A) ? Unsigned(A) A??
• (2) ? operator ???? ,???MSB??,
• ?? 0B
• ?? 1B

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?????

• 2?Std_logic_vector ??
• ??? std_logic_vector ?? Signed or Unsigned ??.
• ? ????????????????
• ??Unsigned?Signed??, ??? downto ??????
• ??? ??packages
• (1) Synopsis Std_logic_arith
• (2) IEEE Numeric_std
• ????Addition -- AIN,BIN8-BIT_std
• Result lt (0unsigned(AIN)(0unsigned(B(IN)
  )Cin
• Cout lt Result (8)
• Note ? ?????,?????????????

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?????

• 3?Bit_vector ??
• Bit_vector ??? unsigned??
• ???
• (1)?Numeric_BIT package ,
• (2)??? bit_vector ?unsigned??
• (3)?????? bit_vector?
• ????
• Sum lt bit_vector( unsigned(AIN) unsigned(BIN))

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??/????? IEEE.Numeric_std

• ??Overload function, ?1076_1993 (1076.3 ,
  Numeric_std)??
• ?????????,type?Signed , unsigned

????
??Function ?? SLL (arg , N) SRL (arg ,
N) ?? Arg signed or unsigned N integer
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??/????? IEEE.Numeric_std
??Function ?? ROL (arg , N) ROR (arg ,
N) ?? Arg signed or unsigned N integer
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??/?????
????
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????? std_logic_std

• SYNOPSYS package std_logic_arith
• Signed extension (????)?????
• SHL SHR
• ?????FUNCTION??????,????Operator
• SHR(A, N) -- Asigned or unsigned ,
  Nunsigned

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?? ??/?????

• ????SYNOPSYS
• LIBRARY IEEE
• USE ieee.std_logic_1164.all
• USE Std_logic_arith.all -------------- Package
• ENTITY Exp_SSHFT IS
• PORT(AIN IN std_logic_vector(3 downto 0)
• BoutL OUT std_logic_vector(7 downto
  0)
• BoutR OUT std_logic_vector(7 downto
  0)
• Ncount in std_logic_vector(1 downto 0))
• END ENTITY EXP_SSHFT
• ARCHITECTURE A OF EXP_SSHFT IS
• BEGIN
• BoutL lt SHL( unsigned(AIN) ,
  unsigned(Ncount))
• BoutR lt SHR(unsigned(AIN) ,
  unsigned(Ncount))
• ----??FUNCTION??
• END A

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Signal Assignment
49
Signal Assignment ??

• Signal Assignment ???Signal type????
• Signal AltB ---?????
• Variable AB ---Variable????Process
  or ????.
• ???
• ???
• (1) assign WhenElse
• (2) IF Then assign Elsif Then assign
  End IF
• ????,????(?????)
• ???
• (1)With sel_name Select assign when ,
  assign when others
• (2)Case sel_name Is When gtassign
  End Case
• Notesel_name??? ? ????,???others

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Multiple-driven Signal

• How do we determine the state of this wire
• Rule to determine resolution function

Driver A
What value ?
What value ?
Driver B
2?1 MUX with tri-state output
(Resolved Signal)
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Conditional Assignment ?????

• Cond_expression?????????????? , ????Assign ???
• Conditional Assignment??????????(???????)?

cond_1 cond_2 S_name
1 x ? Exp_1
0 1 ? Exp_2
0 0 ? Exp_3
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Selective Assignment MUX

• Selected signal Assignment ???MUX????????????????
  ?
• ?????????????

Expression for??? , ???? ?List 1 / 3 / 9
?Range (1 to 4 )
????(Ctl)?????????? ??,???When Others????
53
Concurrent(???)

• ???
• ??????
• S1 lt Expr
• ??? (????????????)
• ??????
• S1 lt Expr1 WHEN Cond1 ELSE
• Expr2 WHEN Cond2 ELSE
• Exprn
• ??? (???????????)
• ??????
• WITH Sel_name SELECT
• S1 lt Expr1 WHEN Value1,
• Expr2 WHEN Value2,
• Exprn WHEN OTHERS
• Note Concurrent, ??????,????

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Sequential(???)

• ???
• ??????
• S1 lt Expr S1 Expr
• ??? (????????????)
• ??????
• IF Cond1 THEN S1 lt Expr1
• ELSIF Cond2 THEN S2 lt Expr2
• ELSE Sn lt Exprn
• END IF
• ??? (???????????)
• ??????
• CASE Sel_name IS
• WHEN Value1 gt S1 lt Expr1
• WHEN Value2 gt S2 lt Expr2
• WHEN OTHERS gt Sn lt Exprn
• END CASE
• Note Sequential , ??????, ???

55
?? ????????
Ture Table Ture Table Ture Table
SEL SEL Y
S1 S0 Y
0 0 A
0 1 B
1 0 C
1 1 D
56
?? ???_???

• --mux_4to1_con.vhd
• LIBRARY IEEE
• USE IEEE.std_logic_1164.ALL
• ENTITY mux_4to1_con IS
• PORT( a,b,c,d IN std_logic
• sel IN std_logic_vector(1 downto
  0)
• y OUT std_logic )
• END mux_4to1
• ARCHITECTURE data_flow OF mux_4to1_con IS
• SIGNAL tmp_a, tmp_b, tmp_c, tmp_d std_logic
• BEGIN
• tmp_a lt a AND NOT sel(1) AND NOT sel(0)
• tmp_b lt b AND NOT sel(1) AND sel(0)
• tmp_c lt c AND sel(1) AND NOT sel(0)
• tmp_d lt d AND sel(1) AND sel(0)
• y lt tmp_a OR tmp_b OR tmp_c OR tmp_d
• END data_flow

57
?? ???_???

• --mux_4to1_con.vhd
• LIBRARY IEEE
• USE IEEE.std_logic_1164.ALL
• ENTITY mux_4to1_con IS
• PORT( a,b,c,d IN std_logic
• sel IN std_logic_vector(1 downto
  0)
• y OUT std_logic )
• END mux_4to1_con
• ARCHITECTURE cond OF mux_4to1 IS
• BEGIN
• Y lt a WHEN sel00 ELSE
• b WHEN sel01 ELSE
• c WHEN sel10 ELSE
• d WHEN sel11 ELSE
• 0
• END cond

58
?? ???_???

• --mux_4to1_con.vhd
• LIBRARY IEEE
• USE IEEE.std_logic_1164.ALL
• ENTITY mux_4to1_con IS
• PORT( a,b,c,d IN std_logic
• sel IN std_logic_vector(1 downto
  0)
• y OUT std_logic )
• END mux_4to1_con
• ARCHITECTURE seq OF mux_4to1 IS
• BEGIN
• WITH sel SELECT
• Y lt a WHEN 00 ,
• b WHEN 01 ,
• c WHEN 10 ,
• d WHEN 11 ,
• 0 WHEN OTHERS
• END seq

59
?? ???_???

• --mux_4to1_seq.vhd
• ?
• ARCHITECTURE data_flow OF mux_4to1 IS
• BEGIN
• PROCESS(a,b,c,d,sel)
• VARIABLE tmp_a, tmp_b, tmp_c, tmp_d
  std_logic
• BEGIN
• tmp_a a AND NOT sel(1) AND NOT sel(0)
• tmp_b b AND NOT sel(1) AND sel(0)
• tmp_c c AND sel(1) AND NOT sel(0)
• tmp_d d AND sel(1) AND sel(0)
• y lt tmp_a OR tmp_b OR tmp_c OR tmp_d
• END PROCESS
• END data_flow

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?? ???_???

• --mux_4to1_seq.vhd
• ?
• ARCHITECTURE cond OF mux_4to1 IS
• BEGIN
• PROCESS(a,b,c,d,sel)
• BEGIN
• IF sel00 THEN Y lt A
• ELSIF sel01 THEN Y lt B
• ELSIF sel10 THEN Y lt C
• ELSIF sel11 THEN Y lt D
• ELSE Y lt 0
• END IF
• END PROCESS
• END cond

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?? ???_???

• --mux_4to1_seq.vhd
• ?
• ARCHITECTURE seq OF mux_4to1 IS
• BEGIN
• PROCESS(a,b,c,d,sel)
• BEGIN
• CASE sel IS
• WHEN 00 gt y lt a
• WHEN 01 gt y lt b
• WHEN 10 gt y lt c
• WHEN 11 gt y lt d
• WHEN OTHERS gt y lt 0
• END CASE
• END PROCESS
• END seq

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COMPONENT(??)
63
Component Concepts

• ??structure style ???? (Netlist type)?????,????
• (1)Component design unit C_name.vhd
• .. ????????. ??????(Model)
• (2)Component declaration
• ???????????, ????(pins)
• ???Entity??(Component??)
• (3)Component instantiation
• ?????? PORT MAP

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Component

• Component model (comp.vhd)
• ( in work package )
• Design-unit model (struc.vhd)
• Entity end entity
• Architecture
• component declaration here
• Begin
• Component instantiation here
• End architecture

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??????

• ???VHDL design-unit Model??
• Entity ???? is
• Port (??????)
• End ????
• Architecture A1 of ???? is
• Begin
• End architecture A1
• P1 P3 Formal name

66
Component ? ? ????

• ?????????(Model)???.vhd
• ????,PORT??????(Model)?Entity????
• ???????????(Model) ???????,
• ??? USE WORK.ALL
• ??????
• ??
• COMPONENT CP_name
• PORT( p1,p2 MODE TYPE
• p3 MODE TYPE )
• END COMPONENT
• P1 P3 Formal name

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Component ? ? ???? (????)

• PORT MAP ?????????
• ????
• U1 Comp_name PORT MAP(????)
• Note S1S3 Physical Name CP_P
  Formal Name
• (1)By Name
• PORT MAP(CP_p1 gt s1,
• CP_p2 gt s2,
• CP_p3 gt s3)
• (2)By Position
• PORT MAP(s1,s2,s3)
• ???????????????OPEN,
• ???? ???1?0 (?????Port initial value??OPEN)

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?? ?????

• ??????
• (1)??????
• Un CP_name PORT MAP(p1, p2, pn)
• (2)??????
• Un WORK.E_name(A_name)
• PORT MAP(p1, p2, pn)

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? ?

• And-Or Design-Unit
• (1)??Model??
• ?AND model
• ?OR model
• (2)And-Or????

70
Example ???????
--Component design unit (or2.vhd) LIBRARY IEEE
USE IEEE.std_logic_1164.all ENTITY or2 IS
PORT ( x,y in, std_logic z
out std_logic ) END or2 ARCHITECTURE a_or2 OF
or2 IS BEGIN z lt x or y END a_or2
--Component design unit (and2.vhd) LIBRARY IEEE
USE IEEE.std_logic_1164.all ENTITY and2 IS
PORT ( x,y in, std_logic z
out std_logic ) END and2 ARCHITECTURE a_and2
OF and2 IS BEGIN z lt x and y END a_and2
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Example ????????
--Design unit (AND-OR.vhd) LIBRARY IEEE USE
IEEE.std_logic_1164.all USE WORK.all ENTITY
and_or IS PORT ( a1,a2,b1,b2 in, std_logic
y out std_logic ) END
and_or ARCHITECTURE A_and_or OF and_or IS
Component and2 PORT ( x,y in std_logic
z out std_logic )
END Component Component or2 PORT (
x,y in std_logic z out
std_logic ) END Component Signal
sa,sb std_logic BEGIN U1 and2 port
map(a1,a2,sa) U2 and2 port map(b1.b2.sb)
U3 or2 port map(sa,sb,y) END A_and_or
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PROCESS
73
PROCESS ??

• PROCESS Statement??? Concurrent Statement
• Statements in a PROCESS are executed
  sequentially. (Sequential Statements)
• ?????(Behavior-description)??????? (Modeling
  complex behavior)
• ?????
• 1. I/O bebavior not easily using CSs.
• 2. Models utilize state information
• 3. Incorporate data structure

74
Process statement

• ??????
• Lable PROCESS (Sensitivity_sig_List)
• process_declaration_item
• (such as Constant, Variable,
  Subprogram
• Not Signal)
• BEGIN
• sequential_statement
• END PROCESS Lable

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Process ??

• Lable ???,?????,??????.?? lable ? END PROCESS
  ?? lable, ?????.
• Sensitivity_List ?????????????(Event),? PROCESS
  statement ??????.?PROCESS??????????????????????
  Sensitivity-list.
• process_declaration_item ??local???
• Variables Static, Initialized once and
  retain their values between process activated
• PROCESS??????, ????????(Combinational-logic)??,
  ?????????(Sequential-logic)??

76
PROCESS Simulation

• Process is executed once at the beginning of
  simulation , then suspended (Automatically)?
• Process is reactivated when listed
  sensitivity-signals are evented?
• Variable value Static
• ?Initialized once only (at the beginning of
  simulation )
• ?Maintains the last value (between process
  activation)

77
Process without sensitivity list

• ????
• (1)Lable PROCESS
• declaration
• BEGIN
• sequential statements
• WAIT ON s1,s2
• END PROCESS Lable
• (2)Lable PROCESS (s1, s2)
• eclaration
• BEGIN
• sequential statements
• END PROCESS Lable
• Note (1) Sensitivity list (2) WAIT
  statement??,
• ????????, ??????.
• ?????????, ?Process????????

78
?? Sequential Circuit ??

• D_latch.. No Else
• Library ieee
• Use ieee.std_logic_1164.all
• Entity D_latch is
• Port(EN, D_in IN std_logic
• Q_out OUT std_logic)
• End entity D_latch
• Architecture a2 OF D_latch IS
• Begin
• Process (EN, D_in)
• Begin
• IF(EN1 ) then
• Q_outltD_in
• End IF
• End Process
• End a2

• D_flip_flopCLKevent
• Library ieee
• Use ieee.std_logic_1164.all
• Entity D_FF is
• Port(CLK, D_in IN std_logic
• Q_out OUT std_logic)
• End entity D_FF
• Architecture a1 OF D_FF IS
• Begin
• Process (CLK, D_in, Nclr)
• Begin
• IF Nclr0 then D_outlt0
• ELSIF (CLKevent and CLK0 )
• then Q_outltD_in
• End IF
• End Process

79
?? Combinational Circuit ??

• Mux2x1
• Library ieee
• Use ieee.std_logic_1164.all
• Entity mux2x1 is
• Port(A, B, S IN std_logic Y OUT
  std_logic)
• End entity mux2x1
• Architecture A3 OF mux2x1 IS
• Begin
• Process (S, A, B)
• Begin
• IF(S1 ) then
• Y lt A
• Else
• Ylt B
• End IF
• End Process

80
?? Design a D-F/F model
D Flip Flop D Flip Flop D Flip Flop D Flip Flop D Flip Flop
CLR PS CLK Qn1 /Qn1
L - - L H
H L - H L
H H ? D /D
H H - Q0 /Q0
81
? ? Sequential?? (D-F/F)

• --d_ff.vhd
• LIBRARY IEEE
• USE IEEE.std_logic_1164.all
• ENTITY d_ff IS
• PORT( d,clk,clr,ps IN std_logic
• q,q_bar OUT std_logic )
• END d_ff
• ARCHITECTURE A OF d_ff IS
• BEGIN
• PROCESS(d,clk,clr,ps)
• BEGIN
• IF(clr0) THEN q lt 0 q_bar lt 1
• ELSIF(ps0) THEN q lt 1 q_bar lt
  0
• ELSIF(clkevent and clk0) THEN q lt
  d q_bar lt not d
• END IF
• END PROCESS
• END A

82
? ? Combinational??Concurrent Process
Full_Adder

• Library ieee
• Use ieee.std_logic_1164.all
• Entity FA is
• Port (In1,In2,c_inin std_logic
• Sum,c_outout std_logic)
• End entity FA
• Architecture A1 of FA is
• Signal s1,s2,s3std_logic
• Begin
• HA1Process(In1,In2)
• Begin
• S1ltin1 xor in2 S2ltin1 and in2
• End process HA1
• HA2Process(S1,c_in)
• Begin
• Sumlts1 xor c_in S3lts1 and c_in
• End process HA2
• OR1Process(S2,S3)
• Begin

83
Passive Process

• ???????
• ?????ENTITY?? Process Statement
• ???
• ????????????????
• ???? ?? Entity????Architecture??????Process?????
  
• Passive Process???Process Statement????
• ??????, ?Passive Process????Entity?,
  ???Process????Architecture??
• Passive Process?????signal assignments ,
  ?????????? Variable-assignment.

84
Sequential StatementsWAIT/NEXT
85
WAIT statement

• Suspends the execution of Process statement
• Formats Process is reactivated at
• WAIT FOR time time interval after current
  time
• WAIT ON sig_event One or more Signal Event
  occur
• WAIT UNTIL condition Condition true

86
Example of Wait

• Wait for 50 nec
• Process suspended now and reactivated after
  50 ns
• Wait on A, B, C
• Process suspended now and reactivated when
• one or more of listed signals is evented
• Wait until AB
• Process suspended now and reactivated When
  AB
• Wait
• Wait forever
• Wait on sig_event after 100 ns
• Wait until condition after 100 ns
• Process suspended now and reactivated When
  
• Either wait for-event (until condition)
  occur
• Or 100 ns time elapsed

87
? ? WAIT

• WAIT UNTIL clk1
• WAIT UNTIL clkevent and clk1
• WAIT UNTIL not clkstable and clk1
• ?????
• ?PROCESS statement?Concurrent
• ??event-driven
• ?clk??event??Process??,

88
? ? Wait statement

• ????
• (1)Lable PROCESS
• declaration
• BEGIN
• sequential statements
• WAIT ON s1,s2
• END PROCESS Lable
• (2)Lable PROCESS (s1, s2)
• eclaration
• BEGIN
• sequential statements
• END PROCESS Lable

89
Wait Waveform Generation

• Library ieee
• use ieee.std_logic_1164.all
• Entity none_overlapped_clk is
• Port(Phi1,Phi2,reset out std_logic)
• End Entity none_overlapped_clk
• Architecture A1 of none_overlapped_clk is
• Begin
• Reset Reset lt 1 , 0 after 5 ns
• Clk_P Process is
• Begin
• Phi1 lt 1 , 0 after 10 ns
• Phi2 lt 0 , 1 after 12 ns ,
  0 after 18ns
• Wait for 20ns
• End process clk_p
• End architecture A1

90
NEXT statement

• Used to stop the current loop iteration
• FORMAT
• NEXT loop_lable WHEN condition
• Operation
• If the condition is true , then
• the current iteration of the loop labeled
  with loop_label (or inner-most) is terminated.

91
EXIT statement

• Similar to NEXT statement
• except that terminate the entire loop
• Format
• EXIT loop_level WHEN condition

92
LOOP StatementFORLOOP / WHILELOOP/ LOOP
93
Loop Statement

• Three type
• 1?Known loop_number
• FOR LOOP END LOOP
• 2?Unknown loop_number
• WHILE LOOP END LOOP
• 3?Simple loop
• LOOP END LOOP

94
FOR LOOP

• Number_count type Loop
• Format
• FOR name IN range LOOP
• sequential statement
• END LOOP
• Note
• 1. namerange must have same type

95
??

• FOR I IN 1 TO 10 LOOP
• A(I) A(I)1
• END LOOP
• --------
• WHILE AltB LOOP
• A A1
• END LOOP

96
WHILE LOOP

• Conditional Loop
• Format
• WHILE condition LOOP
• sequential statement
• END LOOP
• Note
• 1. Never executed if condition is initially
• false

97
Simple LOOP

• Format
• LOOP
• sequential statement
• END LOOP
• Executed continuously, So be insert with EXIT
  staement
• Example
• LOOP
• COMPUTE(x) -- A Function
  named COMPUT
• EXIT WHEN X lt10
• END LOOP

98
Hierarchical DesignParametric Modeling Generics
99
GENERICS

• Design units ????????? ????????????or???
• Enables the construction of parameterized models
• The value of generics must be known at compiling
  time
• Generics are constant objects and can only be read

100
?? ??Delay time ??

• Typical parameter , used in Simulation only
• Inertial delay
• ???Gate-delay ??????
• Z lt x and y After 4 ns
• Transport delay
• ???Path-delay ?????
• Z lt Transport x and y After 4 ns
• Generic ??
• Z lt x and y After delay_time

101
Generics ?? (???????)

• ????Component Model ?entity???
• ??
• GENERIC (gn_name type
  initial_value)
• ??
• ENTITY and2 IS
• GENERIC (t_delay time 4 ns)
• PORT ( x,y in, std_logic z out
  std_logic)
• END Entity and2
• ARCHITECTURE a_and2 OF and2 IS
• BEGIN
• z lt x and y after t_delay
• END ARCHITECTURE a_and2

102
Generics ?? (???????)

• ? ???component?Design unit ?Architecture ?
  component?????
• ??
• COMPONENT and2
• GENERIC (t_delay time 4 ns)
• PORT ( x,y in, std_logic
• z out std_logic)
• END COMPONENT
• Note????????,??component ??????(??????)

103
Generics ?????(default value)?override

• GENERIC MAP
• ?component Instantiation???
• Entity e_name IS
• PORT ( a_name mode, type .)
• END Entity e_name
• ARCHITECTURE a_name OF e_name IS
• COMPONENT and2
• GENERIC (g_delay delay_length 4
  ns)
• PORT ( x,y in, std_logic z out
  std_logic)
• END COMPONENT and2
• BEGIN
• u1 and2 generic map (10 ns) PORT MAP
  (a,b,c)
• END ARCHITECTURE a_name

Map????
By name g_Delay gt 10 ns
104
Generic ---- Default???

• generic map (open)
• ??????
• ????Generic???Override ?,
• ??Component???Default???

105
?? N-Input Gate

• AND gate model different size AND gate
• Entity generic_and is
• generic (n positive 2)
• PORT ( in1 IN std_logic_vector((n-1) downto
  0)
• Y OUT std_logic)
• END Entity generic_and
• ARCHITECTURE a1 OF generic_and IS
• BEGIN
• Process (in1)
• variable and_temp std_logic 0
• Begin
• and_temp 1
• For I in (0 to (n-1) Loop
• and_temp and_temp and in(i)
• End loop
• Y lt and_temp
• End process

106
Generic Length-Parameter

• ??Design-Unit
• a length-parametric P_REG model

107
?? ??P_REG model

• N-bit Register???Model?
• Library ieee
• Use ieee.std_logic_1164.all
• Entity P_reg IS
• Generic (len_size positive 4 )
  ..??len_size ???2
• PORT (CLK, N_rst IN std_logic
• D_inIN std_logic_vector(len_s
  ize-1 downto 0)
• Q_out OUT std_logic_vector(le
  n_size-1 downto 0))
• END Entity P_reg
• ARCHITECTURE a1 OF P_reg IS
• BEGIN
• PROCESS (N_RST, CLK)
• BEGIN
• IF N_RST0 THEN Q_out lt (
  OTHERSgt0 )
• ELSIF ( CLKevent and CLK1 ) THEN
• Q_out lt D_in
• END IF

108
P_REG ???8-bit register (REG_8) model

• -- 8_bit Register Device Model?
• Library ieee
• Use ieee.std_logic_1164.all
• Entity reg_8 IS
• PORT (CLK, N_rst IN std_logic
• D_in IN std_logic_vector(7
  downto 0)
• Q_out OUT std_logic_vector(7
  downto 0))
• END Entity reg_8
• ARCHITECTURE a8 OF reg_8 IS
• Component P_reg
• Generic( len_sizepositive 2) ----
  ???????
• PORT(CLK, N_rst IN std_logic D_in IN
  std_logic_vector(7 downto 0)
• Q_out OUT std_logic_vector(7
  downto 0))
• End Component P_reg
• BEGIN
• U1 P_reg Generic map(8) ---- ???????
• PORT map (CLKgtCLK,N_RSTgtN_RST,D_ingtD_
  in,
• Q_outgt Q_out)

109
Generic_Adder

• Let Xunsigned , Y std_logic_vector
• TYPE conversion (known as Cast )
• ? X lt unsigned (y) Y lt
  std_logic_vector (X)
• VHDL model (???Model?)
• Library ieee
• Use ieee.std_logic_1164.all ---- for integer
  addition
• Use ieee.Numeric_std.all ---- for Signed/
  Unsigned addition
• Entity Adder_n is
• Generic (n Positive 4)
• Port (A,Bin std_logic_vector (n-1 downto 0)
• Sout std_logic_vector (n-1 downto
  0)
• Cinin std_logic Coutout
  std_logic)
• End Adder_n
• Architecture a1 of adder_n is
• signal result, Carry unsigned (n downto 0 )
  ---- type conversion
• Begin
• Carry lt(0gt Cin, Others gt 0 )
  ----cingtCarry(0)

110
16_bit Adder using parameterized Adder

• -- 16_bit adder Device Model?
• Library ieee
• Use ieee.std_logic_1164.all
• Use work.all
• Entity add_16 is
• Port(a,bin std_logic_vector(15 downto 0)
• sout std_logic_vector(15 downto 0)
• cin in std_logiccoutout std_logic)
• End entity add_16
• Architecture a1 of add_16 is
• Component adder_n
• generic (n positive 4)
• Port(a,bin std_logic_vector(n-1 downto 0)
  
• sout std_logic_vector(n-1 downto
  0)
• cin in std_logiccoutout
  std_logic)
• End component
• Begin
• U1 adder_n generic map (16)
• port map (a,b,s,cin,cout)

111
parametric n to 2n decoder model

• Diagram

112
parametric n to 2n decoder model

• N-bit Decoder ???Model?
• Library ieee
• Use ieee.std_logic_1164.all ---- for integer
  addition
• Use ieee.Numeric_std.all ---- for Signed/
  Unsigned addition
• Entity decoder_n is
• Generic (n positive 4)
• Port (Ain std_logic_vector (n-1 downto 0)
• Zout std_logic_vector (2n-1 downto
  0))
• End decoder_n
• Architecture a1 of decoder_n is
• constant Z_out Unsigned (2n-1 downto 0)
  (0gt1, others gt0)
• Begin
• Z lt std_logic_vector sll(Z_out
  to_integer(unsigned (a)))
• End architecture a1

113
Hierarchical DesignRegulated Modeling Generate
114
Generate Statement

• GENERATE statement????
• ???????????(Regular interconnection)???Model
  ?
• ???? Concurrent - statement
• G_label ???-statement
• GENERATE
• Comp_label comp_name PORT MAP(
  )
• END GENERATE

115
Generate ????

• Generate ???-statement , ????
• FOR GENERATE Range define
• IF GENERATE value-define
• ????
• (1). G_label1 FOR I IN low_limit TO hi_limit
• GENERATE
• Comp_label comp_name PORT MAP( )
• END GENERATE
• (2). G_label3 IF I 3
• GENERATE
• Comp_label comp_name PORT MAP( )
• END GENERATE

116
?? A Register model

• Entity reg_8 is
• Port (Din std_logic_vector(7 downto 0)
• Qout std_logic_vector(7 downto 0)
• clkin std_logic)
• End reg_8
• Architecture a1 of reg_8 is
• Begin
• REG For I in drange GENERATE
• U DFF port map ( D(i), Q(i), clk)
• END GENERATE
• End A1

117
?? Design Unit ???Shift-register
(PG_SFT_REG_R) VHDL model
?? (1)Design-Unit DFF VHDL Model is
required (2)A parameterized generated structure
PG_SFT_reg_L model is defind (3)Implement
the shift-register model of a Specified-
length SFT_REG_R8 model
118
parameterized generated structuremodel
PG_SFT_reg_R
Library ieee Use ieee.std_logic_1164.all Ent
ity PG_SFT_reg_R IS Generic (lengthn positive
4) PORT (CLK,NRST IN std_logic D_in IN
std_logic D_out OUT std_logic) End entity
PG_SFT_reg_R Architecture A1 of PG_SFT_reg_R IS
Component DFF port (CLK,NRST,D IN
std_logic Q out std_logic) End
component SIGNAL temp std_logic_vector(1 to
lengthn-1) BEGIN -- define the number of
structur-repeating SFTL_reg FOR I in 1 to
(lengthn) GENERATE Gen_start IF I 1
GENERATE DffL1 DFF PORT MAP (CLK, NRST, D_in,
temp(1) ) End Generate Gen_end IF I
lengthn GENERATE DffL2 DFF PORT MAP (CLK,
NRST, temp(lengthn-1) , D_out ) End
Generate Gen_mid IF( Igt1)and(Iltlengthn)
GENERATE DffL3 DFF PORT MAP (CLK, NRST,
temp(I-1) , temp(I) ) End Generate End
Generate End architecture A1
119
?? 8-bit Shift_register Model using PG_SFT_reg
model
Library ieee Use ieee.std_logic_1164.all Entity
SFT_reg_R8 IS PORT (CLK,NRST, D_in IN
std_logic D_out OUT
std_logic) End entity SFT_reg_R8 Architecture
A1 of SFT_reg_R8 IS Component PG_SFT_reg_R IS
Generic (lengthn positive 8)
Port (CLK,NRST, D IN std_logic Q out
std_logic) End component BEGIN U1
PG_SFT_reg_R GENERIC MAP (lengthn gt 8) PORT
MAP (CLKgtCLK, NRSTgtNRST, DgtD_in,
QgtD_out) End architecture A1
120
?? 8-bit Shift_register Testbench
---- Preceding items aS usually used -- Set the
initial state of the register NRST1 , 0
after 5 nsec , 1 after 10 nsec -- shift test
process Tester Process Variable Test_vector
(7 downto 0) 10110010 Begin For I in
test_vectorrange loop DIN lt
test_vector(i) CLK lt 0 Wait for 5
ns CLK lt 1 Wait for 5 ns End loop
Wait End process Tester
121
State Machine
122
Sequential Logic
???????? -???????

123
State Machine

• State-machine model
• Basic Parts
• (1)Sequential Process (SEQ_P)
• State lt initial_state
• -- Initial-state setting
• State lt Next_state
• -- Clocked state transfer
• (2)Combinational Process (COM_P)
• (1) Output Function
• Output lt express
• (2) Next state Function
• Next_state lt state

124
?? State Machine

• Library IEEE
• Use IEEE.std_logic_1164.All
• Entity state_machine is
• Port (reset, clk,X in std_logic
• Z out std_logic)
• End entity state_machine
• Architecture A1 of state_machine is
• TYPE state_type IS (S0,S1,S2,S3)
• SIGNAL state,next_state state_type
  state_typeleft
• Begin
• SEQ_P Process End process SEQ_P
• Com_P Process End Process Com_P
• .
• End architecture A1

125
Signal States Type

• Signal states declaration
• Enumerated
• Architecture Begin ?
• -- Define state and its type
• TYPE state_type IS (S0,S1,S2,S3)
• SIGNAL state, next_state state_type
• state_typeleft

126
?? Squential Process

• A state machine changes state at a clock edge

SEQ_P Process Begin Wait until
(clkevent and clk1) --- IF N_RST0
then State lt state_typeleft
---initialize Else state lt
next_state End if End Process SEQ_P
127
?? Combinational Process (Output and
Next_state Function) Mealy machine
COM_PProcess (X , state ) Begin Case
state is When s0 gt IF x
0 then ---- Mealy-m next_state
lt s0 Zlt0 Else
next_state lt s1 Zlt1 End IF
When s1 gt IF x 0 then
next_state lt s0 Zlt0
Else next_state lt s1 Zlt1
End IF End case End Process
SEQ_P
????Next_state?Output ????(Mealy)
Case is using for state-branch judge
128
??Traffic Controller Design
State of system TYPE state_type IS (G,R)
SIGNAL state ,next_state state_type
state_typeright -- for safety
129
?? Traffic Controller --- Using single Process
---
Com Process (state, timed , car) is Begin
start_timer lt 0 Case state is -- Case for
next_state and o/p determine When G gt
Major_green lt 1 Minor_green lt 0 If
car 1 then start_timer lt1
next_state ltR Else next_state ltG End
if When R gt Major_green lt 0
Minor_green lt 1 If timed 1 then
next_state ltG Else next_state ltR End
if End Case End Process com End architecture
A1

• Library ieee
• Use ieee.std_logic_1164.all
• Entity traffic is
• port (clk , timed, car in std_logic
• Start_timer , Major_green,
• Minor_green out std_logic)
• End traffic
• Architecture A1 of traffic is
• Type state_type is (G , R)
• Signal state,next_state state_type
• Begin
• Seq Process (clk) is -- clock-driven seq.
• Begin
• If clkevent and clk1 then
• state lt next_state
• End if

130
?? Traffic Controller --- Moor machine ---
Nextstate_p Process (state, timed , car)
is Begin --- Next_State F(I/P ,
Present_state) Case state is When G gt
If car 1 then next_state ltR
Else next_state ltG End if When R gt
If timed 1 then next_state ltG
Else next_state ltR End if End Case End
Process nextstate_p Output_p Process (state,
car) is --- O/P F( Present_state)
Moor-machine Begin start_timer lt 0
If state G then Major_green lt 1
Minor_green lt 0 If car 1 then
start_timer lt 1 End if Else Major_green
lt 0 Minor_green lt 1 End if End
Process output_p End architecture A1

• Library ieee
• Use ieee.std_logic_1164.all
• Entity traffic is
• port (clk , timed, car in std_logic
• Start_timer , Major_green,
• Minor_green out std_logic)
• End traffic
• Architecture A1 of traffic is
• -- for all processes
• Type state_type is (G , R)
• Signal state ,next_state state_type
• Begin
• Seq_p Process (clk) is
• Begin
• If clkevent and clk1 then