Layout-aware Scan-based Delay Fault Testing

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Layout-aware Scan-based Delay Fault Testing

• Puneet Gupta1
• Andrew B. Kahng1
• Ion Mandoiu2
• Puneet Sharma1

http//vlsicad.ucsd.edu
1 ECE Department, University of California San
Diego 2 CSE Department, University of
Connecticut, Storrs
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Outline

• Introduction
• Problem formulations
• Multi-fragment greedy algorithm
• Experiments and results
• Future directions

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Delay Fault Testing

• Delay fault failure of a path to meet timing

• High clock speeds increasing variability
• ?Delay fault testing important

• Pair of vectors required
• Initialization vector
• Launch vector

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Scan-based Delay Fault Testing

• Utilizes standard shift-scan architecture

• Launch vector produced in two ways
• From circuit logic
• ? Functional justification
• From scan chain
• ? Scan justification

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Functional Justification

• Launch vector generated by the circuit logic

• No effect of scan order

• Not all paths testable

1. Scan-in initialization vector

• Difficult to produce vector pairs

2. Give system CLK to generate launch vector
3. Give system CLK, capture result
4. Scan-out result
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Scan Justification

• Launch vector generated by shifting
  initialization vector

1. Scan-in initialization vector

2. Give scan CLK to generate launch vector
3. Give system CLK, capture result
4. Scan-out result
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Increasing Scan Coverage

• Scan order

• Dont cares

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Scan Order Objectives

• Layout driven, coverage oblivious
• QPlace, Boese et al., Kobayashi et al.,

WL 1.22 mm, Cov 56.80

• Coverage driven, layout oblivious
• Gupta et al, Cheng et al,

• Layout Coverage driven
• Our approach

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Outline

• Introduction
• Problem formulations
• Multi-fragment greedy algorithm
• Experiments and results
• Future directions

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Scan Chain Ordering

• Modeled as TSP with flops as cities

• Vector pair incompatible with an edge
• A vector pair is incompatible with an edge eij if
  placing flop j after flop i in the scan chain
  causes it to become unusable
• Formally, vector pair (u, v) is incompatible with
  eij if

u(i)0 v(j)1 where, u Initialization
vector or u(i)1 v(j)0 v Launch vector

• Dummy insertion in an edge makes all vector pairs
  compatible with it

• TSP objective
• Minimize WL MinWL (Boese et al.)
• Minimize dummy for 100 coverage CompleteDFC
  (Gupta et al.)
• This paper Minimize WL Maximize coverage
  MaxDFC

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MinWL (e.g., Boese et al.)

• Given
• Set of n placed flip-flops F, Scan-in SI,
  Scan-out SO
• Find
• Scan chain ordering ? of F ? SI, SO, starting
  with SI ending with SO
• Such that
• Total scan chain length minimized

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CompleteDFC (Gupta et al.)

• Given
• Set of n flip-flops F, Scan-in SI, Scan-out SO
• Set of m delay fault vector pairs ?
• Find
• Scan chain ordering ? of F ? SI, SO, starting
  with SI ending with SO
• Such that
• dummy flops required for 100 coverage
  minimized

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MaxDFC

• Given
• Set of n placed flip-flops F , Scan-in SI,
  Scan-out SO
• Set of m delay fault vector pairs, ? each with a
  weight wt, t ? ?
• Upped bound on dummies, D
• Find
• Scan chain ordering ? of F ? SI, SO, starting
  with SI ending with SO
• Set of alive vector pairs, C
• Such that
• Scan length minimized
• Sum of weights of alive vector pairs maximized
• Vectors pairs incompatible with at most D edges

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Outline

• Introduction
• Problem formulations
• Multi-fragment greedy algorithm
• Experiments and results
• Future directions

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Three Phase MFG - Overview

• Phase I
• Produce D1 short, high coverage scan chain
  fragments
• Based on multi-fragment algorithm for TSP
• Data structures
• Edge-vector incompatibility matrix
• Edge buckets
• Phase II
• Stitch D1 fragments using D dummies minimizing
  WL
• Phase III
• Further reduce scan chain WL

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Three Phase MFG Phase I
initialize edge-vector incompatibility
matrix distribute edges in buckets based on
incompatible vector pairs while fragments gt
dummies1 pop shortest edge eij from first
non-empty bucket if( eij is admissible in tour
) add eij to tour remove vectors incompatible
with eij from edge-vector matrix promote edges
with which removed vectors were incompatible
1?2 0 0 0 0 1
1?3 0 0 1 0 1
2?3 1 0 0 0 0
2?1 0 1 0 0 0
3?1 0 0 0 0 1
3?2 1 1 0 0 0
3?1
2?1
3?2
2?3
1?3
1?2
5 vectors, 0 dummies
edge-vector matrix
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Three Phase MFG Phase I

• Scalability
• Use small edges, w(e) lt T
• If frags lt dummies 1, rerun with
  thresholdM?T
• Quite insensitive to T, M

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Three Phase MFG Phase II

• Target Stitch D1 fragments, minimizing WL

• Approach
• ATSP with fragments as cities

• we ? WL required to connect fragments

• Small cities
• ? Quick even with high quality TSP solver

2
1
3
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Three Phase MFG Phase III

• Target Further reduce scan WL
• Approach
• Create TSP instance with flops as cities
• Throw in edges compatible with all alive faults
• we ? WL of edge e

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Outline

• Introduction
• Problem formulations
• Multi-fragment greedy algorithm
• Experiments and results
• Future directions

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Experimental Flows

• Comparison of three flows
• MinWL (Boese et al.)
• ? Reference min WL tour
• CompleteDFC (Gupta et al.)
• ? Reference full coverage tour
• MaxDFC

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Testcases
Testcase cells flops paths Functional coverage
s38417 6291 1564 552 0.54
s13207 1648 627 49 8.16
s9234 529 145 361 22.71
AES 10465 554 3050 58.03
DES3 3912 128 1404 7.69
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Results s38417

• Wirelength

• Coverage

MinWL
MaxDFC
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Results aes

• Wirelength

• Coverage

MinWL
MaxDFC
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MFG Scalability
Time(s)
MFG Runtime
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Dummy-Coverage Tradeoff

• Proposed ILP formulation

s38417
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Outline

• Introduction
• Problem formulations
• Multi-fragment greedy algorithm
• Experiments and results
• Future directions

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Conclusions

• We proposed an algorithm to simultaneously reduce
  WL and increase delay fault coverage
• Significant increase in coverage with 10-30 WL
  increase
• Explored tradeoff b/w coverage and dummy insertion

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Future Directions

• Extension to multiple scan chains
• Congestion aware scan ordering
• Modifications to use compacted and/or redundant
  vectors

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Thank You