On Selecting Testable Paths in Scan Designs

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On Selecting Testable Paths in Scan Designs

• Yun Shao, Sudhakar M. Reddy Irith Pomeranz
  Seiji Kajihara

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Motivation

• Tests for small delay defects
• Address combinatorial complexity and fault
  coverage issues of path delay fault model

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Approach

• Minimal Testable Path Cover of the CUT
• Select a minimal size set of testable path S,
  such that for each circuit lead l, S contains at
  least one testable path of maximum delay through
  l.

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Minimal Path Covers Earlier Works

• Select at least one longest structural path
  passing through each line
• An exact polynomial time algorithm to find a
  minimum structural cover set Li et al.,
  TCAD89.
• Drawback - Many paths in the structural cover set
  are untestable because of the lack of
  consideration of the testability of selected
  paths.

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Minimal Path Covers Earlier Works (cont)

• Enumerate a limited number of longest paths
  through every line to find a testable path cover
  set
• Enumerate N paths passing through each line until
  a robustly testable path is found Majihi et al.,
  VLSI96
• Select potentially testable paths to cover all
  lines Cheng et al., TCAD96, Murakami et al.,
  ITC00
• Drawback A large number of paths are explicitly
  enumerated during path selection and the run time
  is high.

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Untestable Path Identification

• Non-enumerative untestable path identification
  Kajihara et. al. VLSI 97
• Every path passing through both a b-line (back
  line) and a f-line (front line) is
  unsensitizable.
• The b-line and f-line describing untestable paths
  are referred to as a b-f pair

Outputs
Inputs
f-line
b-line
b-f pair
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Terminology

• Two definitions Park et al. TCAD92
• The Longest Structural Path Delay the maximum
  delay of all structural paths passing through a
  line (without considering the testability of
  paths)
• The Longest Functional Path Delay the maximum
  delay of all testable paths passing through a
  line
• Structural (Functional) Covered - a line covered
  by a structural (testable) path with its longest
  structural (functional) path delay.

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Contributions

• Use delay analysis to estimate the longest
  functional path delay of each line
• Expand a potentially testable path (containing no
  b-f pair) to cover a given line
• Use a branch-and-bound strategy to iteratively
  search for a longest potentially testable path
  through a target line

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Delay Analysis

• We propose an efficient procedure to compute an
  upper bound of the longest functional path delay
  of a line. It includes two passes.
• Estimate the longest functional path delay
  LDPI(l) (LDPO(l)) from the inputs (outputs) to
  every line l
• For a given f-line (b-line), all paths passing
  through its b-lines (f-lines) are excluded when
  computing the longest functional path delay from
  the inputs (outputs) to the line.

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Stepwise Path Expansion

• Objective
• Construct a potentially testable path passing
  through the target line with maximum delay
• Proposed method
• Forward (Backward) Expansion - expanding the
  target line toward the outputs (inputs) without
  including b-f pairs.
• Greedy approach In every forward (backward)
  expansion step an expansion line with the
  greatest LDPO (LDPI) is chosen to expand the
  partial path already constructed.
• Cant guarantee to get a global longest
  potentially testable path in one iteration.

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Stepwise Path Expansion (cont)

• Heuristic 1 Minimum Cover Expansion
• Choose the local expansion that can cover the
  maximum number of yet uncovered lines.
• Heuristic 2 Delay Constrained Expansion
• Search for potentially testable paths with delays
  greater than a specified value Dmin
• Use the delay of the longest potentially testable
  path ever found as a threshold to iteratively
  reduce the search space by looking for paths with
  delay greater than the longest path obtained.

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Stepwise Path Expansion (cont)
b-line
Inputs
f-line
Outputs
f-line
b-line
FFR
backward expansion line
l
forward expansion line
initial PPI
Decision point

• Mark the b-lines and f-lines of the lines
  included in the partial path.
• Select unmarked lines to expand the partial path.
• Backtracking is required when the partial path
  cant be expanded further without including a b-f
  pair.

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Overall Flow

• ATPG is used to check if the selected potentially
  testable path is truly testable.

min_delay 0
Fail
min_cover_expand(l, min_delay)
A
succeed
succeed
untestable
ATPG(p)
next_path(min_delay)
detected
Fail
true
D(p) DP(l)?
B
A
false
min_delay D(p) incr_delay
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Experimental Results (cont)

• Comparing line coverages (with respect to
  coverable lines) for scan designs using
  functional justification (weak non-robust)

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Experimental Results (cont)

• Comparing line coverages (with respect to all
  lines) of weak non-robust tests and strong
  non-robust tests for scan designs using
  Functional Justification

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Experimental Results

• Cover sets for Scan Designs using Functional
  Justification (weak non-robust)

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Conclusions

• Proposed an efficient method to select paths to
  test. The selected set of paths have minimal
  size, are testable and include each circuit line
  in at least one path of maximum delay containing
  the line.
• The run time for the entire procedures including
  test generation time is comparable to that for
  generating tests for the set of selected paths.