Testing Delay Faults in Asynchronous Handshake Circuits

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Testing Delay Faults in Asynchronous Handshake
Circuits

• Feng Shi Yiorgos Makris
• Electrical Engineering Department

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Outline

• Background
• Handshake circuits
• Delay faults in HS circuits
• Two types of delay faults
• Challenges of delay testing
• Proposed methods for delay testing
• Test for performance degradation
• Test for timing constraints
• Experimental results
• Conclusion

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Background

• Asynchronous circuits
• Low power, low EMI, high modularity
• Demonstrated in both academia and industry
• Classes of asynchronous circuits
• Delay-insensitive
• Quasi-delay-insensitive, speed-independent
• Timed circuits
• Testing asynchronous circuits
• Stuck-at faults
• Delay faults

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Handshake Circuits
Developed by Handshake Solutions
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Testing Stuck-At Faults in HS Circuits

• Full-scan based solution te Beest et. al,
  ITC02
• Remove combinational loops
• Scannable state-holding elements
• Scan testable netlist and remodeled netlist
• Scannable C-elements
• High area overhead
• Considerably slower
• A multiplexer based scan te Beest et. al,
  ASYNC05
• Faster Only a multiplexer is in the loop
• Low area overhead
• Optimization opportunities

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Testing Stuck-At Faults in HS Circuits
A mux-based scan c-element
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Testing Stuck-At Faults in HS Circuits
Normal mode se 0
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Testing Stuck-At Faults in HS Circuits
Scan shift mode se 1
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Testing Stuck-At Faults in HS Circuits
Capture mode se 0
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Two Types of Delay Faults

• Only degrade the performance
• Affected component is delay-insensitive
• Gate output delay faults in control block
• Violate the timing constraints
• Isochronic forks
• Bundled data constraints
• Setup and hold timing constraints for
  latches/flip-flops
• For the targeted fault model, such faults only
  exist in datapath.

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Examples of Delay Faults
Only degrade the performance
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Examples of Delay Faults
Violate timing constraints
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Challenges of Delay Testing

• Use synchronous ATE
• Apply test patterns only when the circuit is
  stable
• Observe fault effects only when the circuit is
  stable
• At-speed delay testing
• Necessary to capture the fault effect
• How fast should test clock be applied?
• Switch between test mode and normal mode
• Deterministic fault effects
• Fault effects of a delay fault are not unique
• Autonomous behavior, difficult to derive the
  final results
• Fault effect may be overwritten or disappear
  finally

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Nondeterministic Fault Effects
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Test for Performance Degradation

• Functional test patterns
• Check the performance
• Difficult to automate
• Full-scan based methods (similar to testing
  synchronous circuits)
• Remodel netlist for ATPG after scan insertion
• Select delay fault models
• Generate test patterns under scan shifting mode
• Apply test patterns, use a reference clock to
  capture fault effects

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Test for Timing Constraints

• A two-step test application procedure for
  at-speed test
• Load the state of the control block
• Sensitize and detect the fault in the data path
• An at-speed test method (switching between test
  mode and normal mode instead of using test clock)
• Load the test patterns in scan shift mode
• Capture the fault effect in normal mode
• Shift out the circuit response in scan shift mode

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Test for Timing Constraints

• A DFT method to load the state of the control
  block

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Test for Timing Constraints

• A DFT method to hold the state of the control
  block

Processing Logic
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Test for Timing Constraints

• A DFT method to hold the state of the control
  block

0
HOLD
Processing Logic
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Test for Timing Constraints

• A DFT method to hold the state of the control
  block

1
Open
Processing Logic
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Test for Timing Constraints

• Test difficulty due to the autonomous behavior
• Nondeterministic fault effect
• High test generation complexity
• Fault effect may be overwritten or disappear
  before it can be observed
• Fault may be exercised more than once
• Hazards may exist
• A DFT method to constrain autonomous behavior
• Registers following the fault are clocked only
  once
• Wrong state bits in the control block are
  preserved

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Test for Timing Constraints

• An example handshake circuit from Haste program

Haste program
Gate-level
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Test for Timing Constraints

• An example handshake circuit with hold component

do G then S od
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Test for Timing Constraints

• An example handshake circuit with hold component

do G then S od
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Test for Timing Constraints

• An example handshake circuit with hold component

do G then S od
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Test for Timing Constraints

• Test generation procedure based on DFT
• Select fault model, generate fault list
• Generate test patterns for the remodeled netlist
  of the datapath
• Guard evaluation
• Expression
• Find functional test patterns for the control
  block to exercise the datapath under test
• High-level simulation
• Snapshot the transient state of the control block
• Extract the pattern for the control block

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Experimental Setup

• Implemented based on HS design tool set
• Insert scan chains, insert DFT, remodel netlist
• Identify timing constraints
• Select fault model, generate fault list
• Determine fault type
• For the 1st type of faults, generate tests for
  performance degradation.
• For the 2nd type of faults, generate tests for
  timing constraints
• Validate test patterns

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Experimental Results
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Experimental Results
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Conclusion

• Two types of delay faults in HS circuits
• Only degrade performance
• Violate timing constraints and cause logic error
• Test methods based on scan
• For 1st, using synchronous ATPG methods
• For 2nd, 2-phase test pattern generation
• DFT techniques for testing timing constraints
• Revised Mux-based scan paths for double loads
• Controlled delay chain to hold the state
• Hold components to constraint autonomous behavior
  
• Demonstrate efficiency through experiments