Topic 11: Designing For Testing II

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Topic 11 Designing For Testing II

• SFSU ENGR 852
• Fall 2004
• 11/29

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Chip Level Testing

• Why Design to Make Testing Easier?
• Test cost has risen as a percentage of total
  product cost to in excess of 55 in some cases
  in recent years.
• Design verification and test program generation
  time can be cut by 5-15 if the circuit is made
  testable from the outset.
• The statements by many silicon vendors that up
  to 50 of 'workingASICs do not work in the
  target system because the designs have neither
  been specified nor verified correctly through
  lack of simulation, and have not been tested
  adequately.
• http//www.fabtech.org/features/tap/articles/02
  .281.html

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Present Testing Level

• How Much to Design for Testability?
• Device test typically provides 40-70 fault
  coverage.
• The warnings now stated widely that in excess of
  98 fault coverage is necessary.
• http//www.fabtech.org/features/tap/articles/02
  .281.html

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This Lecture

• Designing For Testability (DFT)
• Ad hoc techniques
• Structured techniques
• Scan path
• Scan-set Architecture
• Boundary scan
• Built-in self-testing (BIST)
• Signature analysis
• Built-in logic block observer (BILBO)

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Chip Testing

• Chip is a black-box
• Only inputs and outputs can be seen. Set inputs,
  watch outputs
• Ease of setting inputs ? Controllability
• Ease of watching outputs ? Observability
• The ease of testing a circuit is its
  Testability
• Combinational blocks are simple(r)
• Sequential blocks are difficult(er)

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Chip Testing

• Steps
• Generate a set of test vectors
• Assume single SA fault
• Fault coverage evaluation
• Does this cover whats important?
• Is this enough?
• Is this too much?

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Chip Testing

• Test vectors
• Method 1
• Pick important faults
• Work backwards to get inputs
• Work forward to get output
• Try inputs, watch outputs
• Method 2
• Randomly select subset of faults
• Same as Method 1

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Ad Hoc Testing TechniquesPartitioning

• Increasing Testability by dividing up circuit

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Ad Hoc Testing TechniquesOff Chip Clock
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Ad Hoc Testing TechniquesBreak Feedback Loops
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Ad Hoc vs Structured Techniques

• Ad Hoc
• Added sometimes during design
• Added sometimes as an afterthought
• Structured
• Must be designed into design from beginning

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Scan Chain

• Scan in State, Check Subsequent States

Scan Data Out
Next State Decoder
Scan Data In
Scan Select
System Clock
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Scan Chain

• Costs
• Design Time (Automated in Most CAD)
• Silicon Overhead (Area)
• Pin Cost (Trouble for Pin Limited Circuits)
• Gains
• Significant Ease of Testing

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Scan-Set Architecture

• When to use
• Full Scan Path not Appropriate
• Uneconomical, wont work in design
• What it is
• Simplified scan chain
• Add separate serial register to use with specific
  nodes only
• Costs less than full scan chain

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Boundary Scan
A boundary scan block at each pin
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Boundary Scan
Electronics Engineering 1998, Cover Story, Cleo
Mui
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Boundary Scan

• Boundary Scan Block Allows
• Pin Testing
• Connect Pins through Shift Register Mode
• External Test
• Internal Test Mode
• Functional Testing
• Slow Speed or Static
• Scan Path-Like Mode
• Set Inputs, Grab Outputs
• Shift out Outputs

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Built In Self-Testing

• Insert logic into circuit to test circuit
• Whys that good?
• Saves pins
• Can access nodes not accessible from pins
• Less disruptive to actual circuit behavior

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Signature Analysis

• For a given state and inputs, the same pattern of
  1s and 0s will appear in the same order at a
  flip-flop for the same number of clock ticks.
  This pattern of 1s and 0s is called that
  flip-flops signature.

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Built-in Logic Block Observer(BiLBO)

• A LFSR is used to compare results with a
  signature.
• Whats a LFSR?
• Ill show you on the board. Its not something
  thats easily explained.