Embedded test tutorial

1
Deterministic forms of
Deterministic forms of
embedded test
embedded test
2
Deterministic forms of embedded test

• Designed for efficient manufacturing test
• Tester applies the test
• The flow is very similar to scan/ATPG
• On-chip hardware facilitates the improved
  efficiency

3
Scan, ATPG, ATE
4
Motivation
Scan test time 23.4s
5
ATPG - test pattern generation process
1. Target faults
2. Generate test cube 1-5
3. Random fill 99-95
4. Stimuli on ATE
5. Response on ATE
6
How many care bits are in a test cube?
7
Scan/ATPG - non-embedded solution
ATE stimuli
ATE reference

• The same width

- the narrower is the bottleneck

• The same frequency

- the lower is the bottleneck

• Mirror images ATE and scan

- inflated data volume
8
Improvements opportunities

• Various forms of semi-embedded test address the
  bandwidth bottleneck in ATE to chip
  communication
• Using different speed of scan shifting (higher
  and lower than ATE)
• Using internally higher number of scan chains
• Compressing input stimuli
• Compacting responses

9
Non-embedded decompression

• Reduction of volume of stored data
• Pseudorandom - BOST
• Weighted random - WRP (IBM)

ATE stimuli
ATE data
10
Stimuli repetition

• Reduced volume of test data
• MISR - signature per pattern
• OPMISR technology, IBM

ATE stimuli
ATE data
11
Replication of stimuli

• Reduced volume and test time
• Broadcast scan
• Illinois scan
• Mentors ATPG

ATE stimuli
12
Stimuli conversion

• Serial to parallel conversion
• Symmetrical response conversion
• Higher ATE / IO frequency
• Shorter test time
• TI, Philips

ATE stimuli
13
Stimuli encoding

• Reduced volume of test data
• Underutilized bandwidth
• Decompressor capacity problem
• LFSR encoding/reseeding, many other schemes

ATE stimuli
ATE data
14
Reseeding of LFSRs
1
Target a group of faults
LFSR
Scan chains
Seed
Test cube
Generation of test cubes for the group of
targeted faults
2
15
Reseeding of LFSRs - Example
LFSR
Phase shifter
Scans
16
Reseeding of LFSRs -Example
LFSR
Phase shifter
Expressions
17
Linear expressions - Example
18
Solving linear equations - Example
c 1 b c f 0 a b c 0 c d e 1 a
b d f 0 a e f 1
c 1 b f 1 a b 1 d e 0 a b d f
0 a e f 1
c 1 b f 1 a f 0 d e 0 a d 1 a
e f 1
c 1 b f 1 a f 0 d e 0 d f 1 e
1
c 1 b f 1 a f 0 d e 0 e f 1 e
1
c 1 b f 1 a f 0 d f 1 e f 0 f
0
19
Solution - seed
a 0 b 1 c 1 d 1 e 0 f 0
20
Reseeding

• For n bit LFSR there are
• n variables and
• at most n linearly independent equations
• The number of encoded positions in scan chains
  does not exceed the size of the LFSR
• Example
• 10 million gate design
• 500k flip-flop design
• 2 fill rate
• 10,000-bit test cube
• Combined required LFSR length gt10,000 bits

21
Continuous flow decompression

• Reduced volume of scan test data and test time
• SmartBIST (IBM), MISR
• Scan Chain Concealment, MISR
• Embedded Deterministic Test (EDT) (Mentor)

ATE stimuli
ATE data
22
EDT architecture
ATE
23
Continuous flow decompressor
x32 x18 x14 x9 1

• Applications PRPG, decompressor, compactor
• High speed one 2-input XOR gate delay
• Maximum internal fanout 2
• Highly modular structure

24
Continuous flow decompressor
Phase shifter

• High speed one 3-input XOR gate delay
• Very low linear dependency in outputs

25
How many positions can be encoded?
Encoded positions
Injected variables
16 channels 128 cells per chain 128 chains
256 chains 512 chains 1024 chains
Decompressor size
26
Continuous flow decompression

• Decompressor initialization

• Scan loading with valid data

27
Compaction - handling of X states

scan



scan
X

• Programmable scan selection handles X states
• No X bounding logic required

28
Compaction - zero aliasing

scan



scan

• Programmable scan selection eliminates aliasing
• Fault coverage computed on compactor outputs

29
Test response compaction
...
...
decoder
pattern mask

• Per pattern programmable scan selection
• Optional per cycle scan masking

30
Compactor driven by decompressor
scan
...
scan
scan
...
scan
scan
...
scan
Deterministically computed and encoded scan
selection
31
EDT Logic - silicon area and testability

• Area
• 20-25 gates per internal scan
• e.g. 160 scans, 4000 gates
• 0.4 in 1Mgate design
• Testability
• automatically generated 20 EDT scan test
  patterns
• 99.5 coverage

32
EDT Design-For-Test flow
Scan Chain Synthesis

Insertion of EDT Test Logic
Optional Boundary Scan

• No modification of system logic
• No test points
• No x bounding logic
• Pattern independent IP

Incremental Synthesis
EDT Pattern Generation
33
Very similar flow to ATPG

• The same
• core logic scan DRC
• fault models stuck, transition, path, IDDQ,
• pattern types combinational, sequential,
  ram_sequential, multiple load
• EDT reuses ATPG
• libraries
• do files ( EDT commands)
• output vector formats
• Similar diagnostic resolution and flow

Scan Chain Synthesis
Insertion of EDT Test Logic
Optional Boundary Scan
Incremental Synthesis
EDT Pattern Generation
34
EDT vs. ATPG - real design
2590
263




4540 patterns 160 scans
4527 patterns 16 scans
16
16
ATPG
EDT
Test cycles 4527 ? 2590 Tester memory 16 ?
4527 ? 2590
Test cycles 4540 ? 263 Tester memory 16 ?
4540 ? 263
35
EDT vs. ATPG tester memory
10 EDT vectors
1 ATPG vector
16
16
36
EDT Example


Gates 2.1M SCs 180K Decompressor 64 bits Max
Specified 1242 X Sources 556 Area
1.31 Coverage 98.79


76
2238 patterns
16

2400 chains
37
Compression Results
Ckt. Gates SCs
A 543K 45K
B 576K 41K
C 1.2M 70K
D 1.2M 62K
E 1.5M 86K
F 2.1M 181K
G 2.6M 129K
H 3.8M 216K
I 10.9M 297K
98.89
98.78
97.04
99.89
99.07
98.92
92
95.53
94.39
TC (FS)
98.70
98.65
96.90
99.79
99.01
98.78
91.85
95.49
94.34
TC (TK)
94.34
51
53
83
50
60
120
21
26
31
Comp.
31
Channels Chains
161600
161600
161600
161600
81600
122400
2157
2146
1104
1104
Max Specified
2462
505
463
816
676
466
940
1430
3174
2462
Xs
33432
139
61
376
259
1943
556
14483
2611
33432
Decomp. Size
64
64
64
64
40
48
20
20
20
20

38
Compression rate
How far can we go?
39
Low pin count testing

D E C OMPRESSOR
C OMPA C TOR
D E C OMPRESSOR
C OMPA C TOR
200 scan chains
ATE
Volume reduction 65X
Compressed Stimuli
Compacted Responses
Compressed stimuli
Compacted responses

• Chip I/O controlled by boundary scan

40
Low pin count testing

D E C OMPRESSOR
C OMPA C TOR
D E C OMPRESSOR
C OMPA C TOR
100 scan chains
Volume reduction 65X
ATE
Compressed Stimuli
Compacted Responses
Compressed stimuli
Compacted responses

• Chip I/O controlled by boundary scan

41
Oversampling - test time reduction

D E C OMPRESSOR
C OMPA C TOR
D E C OMPRESSOR
C OMPA C TOR
100 scan chains
400 scan chains
ATE
Volume reduction 65X
Test time reduction 260X
Compressed Stimuli
Compacted Responses
Compressed stimuli
Compacted responses

• Chip I/O controlled by boundary scan

42
Modular EDT
8 ? 2
43
Burn-in test with EDT

• Easy set-up
• Decompressor driven by constant values
• Clock supplied to decompressor and scan shift

D E C OMPRESSOR
C OMPA C TOR
D E C OMPRESSOR
C OMPA C TOR
1
clock
44
Deterministic forms of embedded test

• Designed for efficient manufacturing test
• The tester conducts the application of test
• The flow is very similar to scan/ATPG
• Based on standard scan
• Can supports the same fault models as ATPG
• No test points required (although can be used)
• No bounding of X states necessary (in EDT)
• On-chip hardware facilitates the improved
  efficiency
• Compression of 50X compared to ATPG possible