Partial Scan Design with Guaranteed Combinational ATPG

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Partial Scan Design with Guaranteed Combinational
ATPG

• Vishwani D. Agrawal
• Agere Systems, Circuits and Systems Research Lab
• Murray Hill, NJ 07974, USA
• va_at_agere.com
• Yong C. Kim and Kewal K. Saluja
• University of Wisconsin, Dept. of ECE
• Madison, WI 53706, USA
• kimy_at_ece.wisc.edu and saluja_at_engr.wisc.edu

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Overview

• 1. Problem statement
• 2. Background and previous work
• 3. Combinational ATPG for general acyclic
  circuits
• Balanced model generation
• Test generation multiple-fault model
• Results
• 4. Special classes of acyclic circuits
• Internally balanced structure
• Balanced structure
• Strongly balanced structure
• Results
• 5. Conclusion

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Problem Statement

• Partial scan design has less DFT overhead, but is
  less desirable than full-scan because it requires
  sequential ATPG
• Problem To devise a combinational ATPG method
  for general acyclic circuits cyclic structures
  can be made acyclic by partial scan

FF1
FF2
FF2
A cyclic circuit
Acyclic partial scan circuit
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Background and Previous Work Models for Acyclic
Sequential Circuits

• Iterative array model (Kunzmann and Wunderlich,
  JETTA, 1990) Logic duplicated as many times as
  sequential depth for combinational ATPG
• Duplicated logic model (Miczo, 1986) Selective
  logic duplication still results in large
  combinational ATPG circuit
• Pseudo-combinational model (Min and Rogers,
  JETTA, 1992) Shorting of flip-flops makes some
  faults combinationally untestable
• Balanced structure (Gupta, et al., IEEETC, 1990)
  A sequential circuit structure with provable
  fault detection by combinational ATPG

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Relevant Results

• Theorem (Bushnell and Agrawal, 2000) A test for
  a testable non-flip-flop fault in a cycle-free
  (acyclic) circuit can always be found with at
  most dseq1 time-frames.
• Balanced circuit (Gupta, et al., IEEETC, 1990)
  An acyclic circuit is called balanced if all
  paths between any pair of nodes have the same
  sequential depth. A test for any testable fault
  in a balanced circuit can be found by
  combinational ATPG.

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Present Contribution Comb. ATPG for General
(Unbalanced) Acyclic Circuits
Generate a balanced model, map faults
Generate a test vector for a target fault using
combinational ATPG
Obtain a test sequence from comb. vector
Simulate circuit to drop detected faults
Yes
More faults to be detected?
No
Done
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An Example
Unbalanced nodes
a
s-a-0
b
FF
dseq 1
Combinational vector
Balanced model
0
a0
s-a-0
0
1
X
1/0
b0
1
a-1
s-a-0
1/0
1/0
1
FF replaced by buffer
b-1
Test sequence 11, 0X
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A Single Fault Model for a Multiple Fault(New)
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Proof of Correctness for the New Model
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Acyclic Circuit Combinational ATPG Example
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ISCAS 89 Benchmark Circuit Result S5378

• Circuit statistics
• Number of gates 2,781
• Number of FFs 179
• Number of faults 4,603

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ISCAS89 Circuits (Acyclic with Partial Scan)
FC cov. (), FC efficiency (), VL vec.
Length, TGT CPU s Sun Ultra
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ISCAS89 Circuits (Acyclic with Partial Scan)
Circuit statistics
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Subclasses of Acyclic Circuits

• Acyclic circuit A sequential circuit without
  feedback

• Balanced (B) circuit A circuit in which all
  paths between any pair of nodes (PIs, POs, gates
  or FFs) have the same sequential depth (Gupta et
  al, IEEETC, 1990)

• Internally balanced (IB) circuit A circuit that
  becomes balanced by splitting of PI fanouts
  (Fujiwara et al., IEEETC, 2000)

• Strongly balanced (SB) circuit A balanced
  circuit which has same depth from any PIs to any
  reachable POs (Balakrishnan and Chakradhar, VLSI
  Design 96)

• Combinational circuit A sequential circuit with
  full-scan

Sequential
Acyclic
SB
Combinational
IB
B
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Number of Scan FFs for Various Subclasses
IB Internally balanced (Fujiwara, IEEETC,
2000) B Balanced (Gupta, et al., IEEETC,
1990) SB Strongly balanced (Balakrishnan and
Chakradhar, VLSI Design 96)
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Fault Coverage for Acyclic Subclasses
ATPG Gentest (Cheng and Chakraborty, Computer,
1989)
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ATPG CPU Seconds for Acyclic Subclasses(Sun
Ultra Workstation)
ATPG Gentest (Cheng and Chakraborty, Computer,
1989)
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Comb. And Sequential Vector Lengths
Acyclic
Balanced
Internally bal.
Strongly bal.
Combinational
VL Number of combinational ATPG vectors CC
Sequential test clock cycles for scan sequences
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Conclusion

• Using a balanced circuit model and combinational
  ATPG, we can generate tests for any acyclic
  sequential circuit with equal or higher fault
  coverage and efficiency than obtained by
  sequential ATPG.

• For acyclic circuits, the new ATPG procedure
  provides comparable fault coverage and efficiency
  with significantly lower DFT ( partial-scan)
  overhead as compared to internally balanced,
  balanced, strongly balanced and combinational
  subclasses.

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Thank you