Register Transfer Level

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Chapter 8

• Register Transfer Level

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Content

• Register Transfer Level (RTL)
• RTL in HDL
• Algorithmic State Machines (ASM)
• Design Example
• HDL Description of Design Example
• Binary Multiplier
• Control Logic
• HDL Description of Binary Multiplier
• Design with Multiplexers

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Register Transfer Level (RTL)

• Large Digital system design modular approach
• modular constructed from digital device, e.g.
  register, decoder, multiplexer etc.
• Register Transfer operation
• The information flow and processing perform on
  the data stored in register
• RTL is specified by the following three
  components
• The set of register in the system
• The operation that are performed on the data
  stored in the register
• The control that supervises the sequence of
  operation in the system

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Register

• Register is constructed from F.F. and gates
• 1 F.F. gt1 bit register
• N F.F. gtn bit resister
• Register can perform set, cleared, or complement

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Data processing in register

• performed in parallel during one clock
• The result may replace previous data or
  transferred to another register
• For example
• counter
• Shift register

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Statements of RTL

• Transfer R2?R1
• Conditional statement
• if (T11) then(R2 ? R1)
• if(T11)then(R2 ? R1, R1 ? R2)
• Other
• R1 ?R1R2
• R3 ?R31
• R4 ?shr R4
• R5 ? 0

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RTL in HDL

• Digital system can be described in RTL
• By means of HDL
• Verilog HDL
• RTL description use a combination of behavior and
  data flow

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The transfer statement of Verilog HDL (without a
clock)

• Continuous statement
• Procedural assignment (without a clock)

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The transfer statement of Verilog HDL (with a
clock)

• Blocking use as transfer operator
• executed sequentially
• non-blocking use lt as transfer operator
• executed on parallel

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HDL operators

• Arithmetic ?- ? ? / ?
• Logical ? ?!
• Logic ? ? ?
• Bitwise or reduction
• Relationalgt ? lt ? ? ! ? gt ? lt
• True or false
• Shift gtgt ? ltlt ? ,

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Loop statement

• Repeat,Forever,While,For
• Must appear inside an initial or always block

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Logic Synthesis

• The automatic process of transforming a
  high-level language description such as HDL into
  an optimized netlist of gates that perform the
  operations specified by the source code
• Designers adopt a vendor-specific style suitable
  for particular synthesis tools
• HDL constructs used in RTL description can be
  converted into gate-level description

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Example of synthesis from HDL to gate structure

• Assign
• assign Y S ? I1I0
• Is interpreted as a multiplexer of 2-to-1
• always
• may imply a combinational or sequential circuit
• always _at_ (I1 or I0 or S)
• if (S) YI1
• else YI0
• Always _at_ (posedge clock)
• Always _at_ (negedge clock)

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Process of HDL simulation and synthesis
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Algorithmic State Machine

• Logic design can be divided into two part
• The digital circuits that perform the data
  processing operation
• Control circuits that determines the sequence in
  which the various actions are performed

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Algorithmic State Machine (ASM)

• A special flowchart that has been developed
  specifically to define digital hardware
  algorithms
• Resembles a conventional flowchart, but is
  interpreted somewhat differently.
• conventional sequential
• ASM
• sequence of even
• timing relationship between the states of
  sequential controller
• even occurs while going from one state to the
  next
• Three basic elements state box, decision box,
  conditional box

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State box

FIGURE 8.3 ASM chart state box
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Decision box
FIGURE 8.4 ASM chart decision box
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Conditional box
FIGURE 8.5 ASM chart conditional box
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ASM block

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ASM chart and state diagram

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Timing consideration

• Major difference between conventional flow chart
  and a ASM chart is in interpreting the time
  relation among the various operation
• ASM considers the entire block as one unit.

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Design example

• Two F.F. E and F
• A 4-bits binary counter A (A4,A3,A2 and A1)
• A start signal S (starting by clearing A and F)
• S1, increment counter
• A3 and A4 determine the sequences of operations
• If A3 0, E is clear to 0, count continues
• If A3 1,E is set to 1,then if A4 0, the count
  continues, but if A4 1, F is set to 1 on next
  clock pulse and system stops counting
• Then if S 0, the system remains in the initial
  state, but if S 1, the operation cycle repeats.

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ASM chart
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Table 8-2

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Datapath for Design Example

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RTL Description
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State table for control

• Two F.F. G1 and G2

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Logic diagram of control
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HDL Description
HDL Example 8-2 //RTL description of design
example (Fig.8-11) module Example_RTL
(S,CLK,Cir,E,F,A) //Specify inputs and outputs
//See block diagram Fig. 8-10 input
S,CLK,Cir output E, F output 41 A //Specify
system registers reg 41 A //A
register reg E, F //E and F
flip-flops reg 10 pstate, nstate
//control register //Encode the states parameter
TO 2'b00, Tl 2'b01, T2 2'b11 //State
transition for control logic //See state diagram
Fig. 8-11(a)
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always _at_(posedge CLK or negedge Clr) if (Clr)
pstate TO //Initial state else pstate lt
nstate //Clocked operations always _at_ (S or A
or pstate) case (pstate) TO if (S) nstate
Tl else nstate TO Tl if (A3 A4)
nstate T2 else nstate Tl T2 nstate
TO endcase //Register transfer operations //See
list of operation Fig.8-11(b) always _at_ (posedge
CLK) case (pstate) TO if (S) begin
A lt 4'bOOOO F lt 1'bO
end Tl begin A lt A
1'b1 if (A3) E lt 1'bl else
E lt 1'b0 end T2 F lt
I'bl endcase endmodule
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Testing the design description

• HDL Example 8-3
• //Test bench for design example
• module test_design_example
• reg S, CLK, Clr
• wire 41 A
• wire E, F
• //Instantiate design example
• Example_RTL dsexp (S,CLK.Clr,E,F,A)

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Example_RTL dsexp (S,CLK.Clr,E,F,A) initial begin
Cir 0 S 0 CLK 0 5 Clr 1 S
1 repeat (32) begin 5 CLK
CLK end end initial monitor("A b E b F
b time 0d". A.E.F,time) endmodule