Register-Transfer Level Components in Verilog

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Register-Transfer Level Components in Verilog
CS 153, Spring 2007 Ian G. Harris Department of
Computer Science University of California Irvine
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Next Assignment Div/Mod, Structurally

• Need to reimplement the Div/Mod structurally, not
  behaviorally
• Build it using RTL (datapath) components
• Need to determine how to implement behavioral
  operations structurally

• Some tips
• Fixed length loops can be implemented with down
  counters and zero detectors
• Left/right shift can be implemented using shift
  registers
• Assignments within conditionals can be
  implemented using multiplexers to drive registers

if (x gt y) z 1 else z 0
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RTL Components

• Built from gates and flip-flops
• Operate on words rather than bits
• Some are combinational, some are sequential
• Data inputs vs. control inputs
• Data outputs vs. status outputs

Example 8 bit ALU Inputs - in1 70, in270,
op30 Outputs - out70, cout
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RTL Component Design

• Define your RTL components behaviorally, not
  structurally
• Combine RTL components structurally to create a
  larger design

Example 4 to 1 Multiplexer
module mux4to1 (W, S, f) input 03 W, 10
S output f reg f always _at_(W or S) case (S)
0 f W0 1 f W1 2 f
W2 3 f W3 endcase endmodule
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Sequential Components
module reg8 (D, Clock, Resetn, Q) input 70
D, Clock, Resetn output 70 Q reg 70
Q always _at_(negedge Resetn or posedge Clock)
if (!Resetn) Q lt 0 else
Q lt D endmodule

• Reset is negatively asserted
• You can add a clear or a shift function as needed

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Components needed for a Div/Mod

1. Register, 8 bit, needs a load signal
2. Shift register, 8 or 16 bit, needs a load signal
3. Subtractor, 8 bit
4. Comparator
5. Multiplexer, 8 bit, 2 way
6. Counter - to stop after 8 iterations
7. Comparator (or zero detector) - to detect last
   iteration

• Notice that Div/Mod is sequential
• Your testbench will need to generate a clock