VHDL

1
VHDL

• A COMPREHENSIVE TUTORIAL

2
Intended Coverage

• Introduction
• System design approach with HDLs
• History of VHDL
• Why VHDL ?
• Simulation Fundamentals
• Simulation Cycle
• Digital Simulator
• Modeling of Hardware
• Language Basics
• Building Blocks in VHDL
• Design Units and Libraries

3
Intended Coverage(contd.)

• Objects and Data Types
• Structural Description
• Basic Features
• Configuration Specification
• Configuration Declaration
• Behavioral Description
• Process Statement
• Behavioral Modeling - Sequential View
• Behavioral Modeling - Concurrent View
• Dataflow Description
• Complete Example

4
Introduction

• System Design Approach with HDLs
• HDL is mostly related to the front end part of
  the design flow where a system is described with
  programming language constructs.
• A complex system can be easily decomposed into
  smaller pieces improves modularity
• Allows a design to be simulated and synthesized
  before being manufactured.
• Eliminates hardware prototyping expenses
• Reduces design time
• Increases design reliability at lower costs/time
  req.

5
Introduction(contd.)

• Typical Design flow

Algorithm
Level of abstraction
HDL Description (Behavioral) Register Transfer
Level
simulation and verification
Synthesizer
Structural Description
Technology mapping (with ready-made primitives)
Floor Planning
Physical Layout
6
Introduction(contd.)

• Why VHDL ?
• Public Availability
• Developed initiated under Government Contract
• Now is an IEEE standard
• Design Methodology and Design Technology Support
• Technology and Process Independent
• Wide Range of Descriptive capabilities
• Digital System (e.g. box) level to gate level
• Capability of mixing descriptions
• Design Exchange
• Large Scale Design and Design re-use

7
Simulation Fundamentals

• Purpose of simulation is to verify the behavior
  of a system by applying stimulation at the inputs
  and monitoring the response of the system over a
  period of time.
• There are three types of simulators
• Purely analog simulator.
• A simulator with both digital and analog
  simulation capabilities.
• Purely digital simulator.
• In digital simulation only logic level of the
  measured quantity is determined no precise value
  is required.
• In analog simulation the precise values of the
  measured quantities are determined

8
Simulation Fundamentals(contd.)

• The system is described with a Hardware
  Description Language (HDL). The design contains a
  number of concurrently operating blocks connected
  with each other by signals.
• Maintains node values at logic level.
• Maintains a time wheel to model propagation of
  time.
• Evaluates circuit behavior at intervals of time.
  The interval is chosen as the smallest unit of
  time after which a node can change its state.

9
Modeling Hardware

• The VHDL Language
• A language for describing digital and analog
  systems.
• Makes no assumptions about the technology.
• Multiple levels of abstraction for modeling
• Behavioral
• Structural
• Dataflow
• Behavioral model, timing model and structural
  model are integrated.
• A VHDL process models a block and a VHDL signal
  models the connection between different blocks.

10
Structural Model

• Digital circuits consist of components and
  interconnection between them
• A component can in turn be composed of
  sub-components and their interconnections
• A component interacts with other components
  through pins
• Component is modeled as entity
• Component pins are modeled as ports
• Interconnections between components are modeled
  as signals

11
Behavioral Model

• The behavior of a component is modeled inside an
  architecture body of the entity
• It may be described using a collection of
  concurrently executing statements
• A concurrent statement is sensitive to a set of
  input signals and is executed whenever any of its
  sensitive signal changes its value
• A concurrent statement called process statement
  can contain one or more sequential statements
• A set of sequential statements can be clubbed
  together in a subprogram

12
Dataflow Model

• The flow of data through the entity is modelled
  primarily using concurrent signal assignment
  statements.
• The structure of the entity is not explicitly
  specified but it can be implicitly deduced.
• Architecture MYARCH of MYENT is
• begin
• SUM lt A xor B after 8ns
• end MYARCH

13
A simple Example

• entity Xor_gate is
• port (in1, in2 in bit Out1 out bit)
• end Xor_gate
• architecture behavioral of Xor_gate is
• begin
• process
• begin
• Out1 lt In1 xor In2
• wait on In1, in2
• end process
• end behavioral

14
VHDL Libraries Design Units

• A VHDL library is a host dependent storage
  facility for intermediate-form representations of
  analyzed design units
• A design unit is a VHDL construction that can be
  independently analyzed and stored in a design
  library. A design unit may be a primary or a
  secondary one.
• Primary design unit
• entity decl, package decl and configuration decl
• Secondary design unit
• architecture body and package body
• In a library, there can be only one primary unit
  of same name but there can be multiple secondary
  units by same name
• A secondary unit can have name same as primary
  unit

15
Building Blocks in VHDL

• Entity Declaration
• generic, port, declarations, statements
• Architecture Body
• declarations, statements
• Subprogram Declaration
• parameter - list
• Subprogram Specification
• declarations statements
• Package Declarations
• declarations
• Package Bodies
• declarations, subprogram body

16
ENTITY

• provides a name to the component
• contains the port definitions in the interface
  list
• can contain some generic definitions which can be
  used to override default values
• entity identifier is
• generic interface_list
• port interface_list
• declarations
• begin
• statements
• end entity identifier

17
Example

• entity Adder is
• port ( A in Bit
• B in Bit
• Sum out Bit
• Cout out Bit )
• end Adder

A
Sum
Adder
Cout
B
18
Architecture

• encapsulates the behavior and timing information
• contains a number of concurrent statements
• there can be multiple architecture bodies for a
  given entity
• architecture identifier of entity_name is
• declarations
• begin
• statements
• end architecture identifier

19
Example-1

• architecture Behavioral_Desc of Adder is
• begin
• process (A, B)
• Sum lt A or B after 5 ns
• Cout lt A and B after 6 ns
• end process
• end Behavioral_Desc

20
Example-2

• architecture Struct_Desc of Adder is
• -- declarations
• component Or_Comp
• port ( X in Bit Y in Bit Out
  out Bit)
• end component
• component And_Comp
• port ( X in Bit Y in Bit Out
  out Bit)
• end component
• begin
• -- component instantiations
• A1 Or_Comp port_map ( X gt A, y gtB, Out
  gt SUM)
• B1 And_Comp port_map ( X gt A, y gtB, Out gt
  Cout)
• end Struct_Desc

21
Subprograms

• Subprograms are of two types
• functions and procedures
• A subprogram consists of a sequence of
  declarations and statements which can be repeated
  from different locations in VHDL descriptions
• subprograms can be overloaded
• functions can be used for operator overloading
• procedures can assign values to its parameter
  objects while functions can not
• A subprogram can be separated into its subprogram
  declaration and subprogram body

22
Subprograms (contd.)

• Full form of subprogram declaration is
• subprogram-specification
• Two forms of subprogram - specification
• procedure identifier interface_list
• pure impure function identifier
  interface_list return
• 
  type_mark
• Full form of subprogram body is
• subprogram-specification is
• declarations
• begin
• statements
• end identifier

23
Functions

• Intended to be used strictly for computing values
  and not for changing value of any objects
  associated with the functions formal parameters
• All parameters must be of mode in and class
  signal or constant or File.
• If no mode is specified, the parameter is
  interpreted as having mode in. If no class is
  specified parameters are interpreted as being of
  class constant. Parameter of type FILE has no
  mode.
• Examples of function declaration
• Object class of parameter is implicit
• function Mod_256 (X Integer) return Byte
• Object class of parameter is explicit
• function Mod_256(constant X in Integer) return
  Byte

24
Example

• Function declaration
• function Min (X, Y Integer) return Integer
• -- Function Specification
• function Min (X, Y Integer) return Integer is
• begin
• if (X lt Y) then
• return X
• else
• return Y
• end if
• end Min

25
Procedures

• Procedures are allowed to change the values of
  the objects associated with its formal parameters
• Parameters of procedures may of mode in, out or
  inout
• If no mode is specified the parameter is
  interpreted as having mode in. If no class is
  specified parameters of mode in are interpreted
  as being of class constant and parameters of mode
  out or inout are interpreted as being of class
  variable. Parameter of type FILE has no mode.
• Examples of procedure declaration
• Object class of parameter is implicit
• procedure Mod_256 (X inout Integer)
• Object class of parameter is explicit
• procedure Mod_256(variable X inout Integer)

26
Example

• Procedure declaration
• --- X is of class variable
• Procedure ModTwo (X inout Integer)
• -- Procedure Specification
• Procedure ModTwo (X inout Integer) is
• begin
• case X is
• When 0 1 gt null
• When others X X mod 2
• end case
• end ModTwo

27
Packages

• Allows data types, subprograms, object
  declarations (signal, constants, shared variables
  and files), component declarations etc. to be
  shared by multiple design units.
• package identifier is
• declarations
• end package identifier
• Example
• package logic is
• type Three_level_logic is (0, 1, z)
• function invert (Input Three_level_logic)
  return
• 
  Three_level_logic
• end logic

28
Package Body

• Package declarations and bodies are separately
  described
• Package declarations contain public and visible
  declarations
• Items declared inside package body is not visible
  outside the package body
• Package body has the same name as the
  corresponding package declaration
• package body identifier is
• declarations
• end package body identifier

29
Package Body (contd.)

• Example of a package body for package logic
• package body logic is
• -- subprogram body of function invert
• function invert (Input Three_level_logic)
  return
• Three_level_logic is
• begin
• case Input is
• when 0 gt return 1
• when 1 gt return 0
• when Z gt return Z
• end invert
• end logic

30
USE CLAUSE

• Use clause preceding an unit makes all the
  elements of a package or a particular element of
  a package visible to the unit
• An architecture body inherits the use clauses of
  its entity. So if those use clauses are
  sufficient for the descriptions inside the
  architecture, then no explicit use clause is
  necessary for the architecture
• Simple examples
• Makes all items of package std_logic_1164 in
  library ieee visible
• use ieee.std_logic_1164.all
• Makes Three_level_logic in package Logic in
  library work visible
• use work.Logic.Three_level_logic

31
Use Clause (contd.)

• library my_lib
• use my_lib.Logic.Three_level_logic
• use my_lib.Logic.Invert
• entity Inverter is
• port (X in Three_level_logic
• Y out Three_level_logic)
• end inverter

32
Analysis Rules for Units

• Units can be separately analyzed provided
  following rules are obeyed
• a secondary unit can be analyzed only after its
  primary unit is analyzed
• a library unit that references another primrary
  unit can be analyzed only after the referred unit
  has been analyzed
• an entity, architecture, configuration referenced
  in a configuration declaration must be analyzed
  before the configuration declaration is analyzed
• A library clause makes library visible and an use
  clause makes the units inside the library
  visible to other units
• library Basic_Library
• Use Basic_Library.Logic
• Use Logic.all

33
Objects and Data Types

• Something that can hold a value is an object (e.g
  signal)
• In VHDL, every object has a type, the type
  determining the kind of value the object can hold
• VHDL is strongly typed language
• The type of every object and expression can be
  determined statically. i.e the types are
  determined prior to simulation.
• Three basic VHDL data types are
• integer types
• floating point types
• enumerated types
• Data types can be user defined

34
Data Types
Data type

Scalar Type
Composite Type
Access Type
File Type
Record
Integer
Float
Array
Physical
Enumeration
Integer and enumeration types are called discrete
types
Integer, Real and Physical types are called
numeric types
35
Data Types(contd.)

• Scalar Type
• Most atomic
• Can be ordered along a single scale
• Integer types
• type Byte is range -128 to 127
• type Bit_pos is range 7 downto 0
• Floating types
• type fraction_type is range 100.1 to 200.1
• Enumerated Types
• consists of enumeration literal
• a literal is either an identifier or a character
  literal
• type Three_Level_Logic is (0, 1, z)
• type Color_set is (RED, GREEN, BLUE)

36
Data Types Scalar Type (contd.)

• Physical Type
• Values of physical type represent measurement of
  some physical quantity such as time, distance
  etc.
• Any value of a physical type is an integral
  multiple of the primary unit of measurement for
  the type
• Example
• type Time is range -(231 -1) to (231
  -1)
• units
• fs ---
  primary unit
• ps 1000 fs --- secondary
  unit
• ns 1000 ps --- secondary
  unit
• end units

37
Literal

• These are symbols whose value is immediately
  evident from the symbol
• Six Literal Types
• integer, floating, characters, strings,
• bit_string and physical literal
• Examples
• 2 19878 16D2
  8720 21000100
• 1.9 65971.3333 843.6e4
  43.6E-4
• ABC()
• B1100 XFf O70
• 15 ft 10 ohm 2.3 sec

38
Composite Types

• Composite type are used to define collection of
  values
• Can be decomposed into smaller atomic types
• Composite Types are of two types
• Records
• Arrays

39
Records

• Records - heterogeneous composite
• Record Type definition specifies one or more
  elements, each element having a different name
  and possibly a different type.
• Example
• type OpCode is (add, sub, compl)
• type address is range 160000 to 16FFFF
• type instruction is
• record
• Opc_field OpCode
• Op1 Address
• Op2 Address
• end record

40
Arrays

• Arrays - homogenous composite type
• type Word is array (15 downto 1) of Bit
• Can have multiple dimensions
• type Arr2Dim is array
• (integer range1 to 3, integer range 5 to 7) of
  integer
• Each dimension must be of discrete type
• integer or enumerated
• Can be constrained or unconstrained
• constrained array has bounds specified
• unconstrained array has no bounds specified

41
Constrained Arrays

• The type and range are both specified by discrete
  range
• Two Forms
• simple range specification
• type Word is array (15 downto 1) of Bit
• type Severity_level_stats is array(Note to
  Failure) of Integer
• range is a subtype indication
• type Column is range 1 to 80
• type Row is range 1 to 24
• type Matrix is array (Row, Column) of Boolean
• type Matrix is array (Row range 1 to 10, Column
  range 1 to 40 ) of Boolean

42
Unconstrained Arrays

• The type of each dimension is given but range
  bounds and direction is not specified
• type Screen is array (Integer range ltgt, Integer
  range ltgt) of Pixel
• Two predefined unconstrained array
• type Bit_vector is array (Natural range ltgt) of
  Bit
• type String is array (Positive range ltgt) of
  Character
• Useful in defining interface list having variable
  number of bits in ports

43
Aggregates

• Values of composites can be given in aggregate
  notation
• An aggregate is a parenthesized list of element
  associations each element specifies values of an
  element of the array or the record
• Value association may be named or positional
• Examples
• (155, 203) (1, 0, 0) -- positional
• (Numerator gt 155, Denominatorgt200) -- named
• ( Low Falling gt 0) -- named

44
Access Type

• Values belonging to an access type are pointers
  to a dynamically allocated object of some other
  type. They are similar to pointers in Pascal or C
  language.
• The objets of an access type can only belong to
  variable class. When an objet of access type is
  declared, the default value of that objet is
  null.
• Example
• type module is record
• size integer
• delay time
• end record
• type PTR is access module --- access type
  declaration
• variable MOD_PTR PTR --- access
  variable, default null

45
File Type

• Objects of FILE types represent files in the host
  environment
• Provides a mechanism by which a VHDL design may
  communicate with host environment
• A file can be opened, closed, read, written to,
  or tested for an end-of-file condition by using
  special procedures and functions that are
  implicitly declared for every FILE type
• Example
• type intFileType is file of integer
• file F1 intFileType
• file F2 intFileType is myFile.txt

46
Pre-Defined Types

• Each implementation can define range of
  pre-defined types differently
• Scalar Types
• type Integer is -(231 - 1) to (231 - 1)
• type Real is -160.7FFF_FF8E32 to
  60.7FFF_FF8E32
• type Boolean is (False, True)
• type Bit is (0, 1)
• type Severity_Level is (Note, Warning, Error,
  Failure)
• type Character is (NUL, SOH, ...., a, b,
  ....., DEL)
• Composite Types
• type Bit_vector is array (Natural range ltgt) of
  Bit
• type String is array (Positive range ltgt) of
  Character

47
Referencing Elements of Composite

• Can be referenced in entirety or by element
• An indexed name is used to refer to an element
• The type of an indexed name is the type array
  element
• A slice name is a reference to a contiguous
  subset of elements in an one-dimensional array
• Examples
• type Byte is array (7 downto 0) of Bit
• type S_memory is array (0 to 216 -1) of Byte
• signal S_byte Byte
• signal S_mem S_memory
• S_byte (3 downto 1) --- slice of
  three elements
• S_mem (215 -1 to 216 -1) --- slice of 215
  elements
• S_mem (0) (0 downto 0) --- slice of one
  element

48
Subtypes

• A subtype is a type with a constraint
• A value belongs to a subtype of a given type if
  it belongs to the type and satisfies the
  constraint
• The given type is called the base type of the
  subtype
• Subtypes of a type are fully compatible with each
  other
• Two ways to constraint a type by a subtype
• a range constraint that defines a subset of
  values of a scalar type
• subtype LowerCase is Character range a to z
• to specify an index constraint of a array
  dimension of unconstrained type
• subtype Register is Bit_Vector (7 downto 0)

49
Attributes

• Attribute is a named characteristic
• It may belong to the following classes of items
  in VHDL
• type, subtypes
• procedure, functions
• signals, variable and constants
• entities, architectures, configurations and
  packages
• components
• statement labels
• literal, unit, group, file
• A particular attribute for a particular item may
  have a value, and if it does have a value, the
  same may referenced as
• name attribute_identifier
• Attributes may be pre-defined or user-defined

50
Attributes (contd.)

• Pre-defined attributes for scalar subtypes
• left, right, high, low
• Example
• type Bit_position is range 15 downto 0
• Bit_positionleft 15
• Bit_positionlow 0
• Bit_positionright 0
• Bit_positionhigh 15

51
Attributes (contd.)

• Pre-defined attributes for any physical subtype
  or any discrete subtype
• pos, val, succ, pred, leftof, rightof
• Example
• Bit_positionpos(15) 15
• Bit_positionval(15) 15
• For any physical or discrete type T
• Tsucc(x) Tval(Tpos(x) 1)
• Tpred(x) Tval(Tpos(x) - 1)
• For a physical or discrete type T, with ascending
  range
• Trightof(x) Tsucc(x)
• Tleftof(x) Tpred(x)
• Pre-defined attributes for constrained array
  subtypes and array objects
• left, right, high, low, length, range,
  reverse_range

52
Attributes (contd.)

• User Defined Attribute
• Attribute declaration
• syntax attribute identifier type_mark
• type int_type is range 1 to 100
• attribute INDEX int_type
• Attribute Specification
• associates a user-defined attribute with one or
  more named entities and defines a value of that
  attribute of that attribute for that named entity
• signal Cin, Cout int_type
• attribute INDEX of Cout signal is 5
• attribute CAPACITANCE of all signal is 10 pF

53
Attributes (contd.)

• Example
• entity att_example is
• end
• architecture att_example of att_example is
• subtype int_subtype is integer range 1 to
  100
• signal s1, s2, s3 int_subtype
• --- attribute declaration
• attribute SIG_NUM int_subtype
• --- attribute specification
• attribute SIG_NUM of s1 signal is
  1 --- for s1 only
• attribute SIG_NUM of others signal is 3
  --- for s2, s3
• begin
• --- accessing the attribute value
• s1 lt s3SIG_NUM --- assigns value 3 to
  signal s1
• end

54
Objects

• Four types of objects
• signals, variables, constants and files
• Signals and variables can be assigned values in
  succession. Constants are assigned only once.
• Signals are like wires.
• Variables have no hardware equivalent.
• A file declaration declares a file of specified
  type.
• Every object must be of a type and has to be
  defined in its declaration.
• constant ROM_size integer 16FFFF
• variable fetch Boolean TRUE
• variable address integer range 0 to
  ROM_size 10
• signal enable Bit 0
• type integer_file is file of integer
• file F1 integer_file is
  test.txt

55
Objects (contd.)

• Following are Implicitly defined Objects
• Generics - constants
• Ports (entity, components, blocks) - signals
• Subprograms
• Function Parameters -
• - Mode should be in.
• - Object class must be constant, signal or
  file.
• Procedure Parameters -
• - Mode should be in, out or inout.
• - Object class may be constant, signal,
  variable or file.
• Indexes of Loop and Generate statements
• - Within the sequence of statements
  these are
• considered as constants and hence
  cant be
• modified.

56
Interface Lists

• Specifies interfaces or potential points of
  communication between units.
• Four VHDL constructs that specify this
• entity declaration, local component declaration,
  block statement and subprogram specification
• Each interface element declares one or more
  interface objects.
• The object in a single interface element have
  three properties in common
• Object Class signal, constant, variable or file
• Mode in, out, inout, buffer(for
  ports only) or
• linkage(for ports
  only)
• Data type

57
Association Lists

• Actual communication path between separate units.
• Four VHDL constructs that specify this
• Component instantiation statement
• binding indication
• block statement
• subprogram call
• Association may be named or positional.

58
Structural Description

• Basic Features
• Component Instantiation Statement
• It is concurrent statement. It can be done by -
• Instantiation of a declared Component
• A component is instantiated. The component
  needs to be bound to some actual
  entity(architecture) with a configuration.
• Direct instantiation statement (VHDL 93 feature)
• No component needs to declared. No separate
  binding is required. An entity(architecture) can
  be directly instantiated.
• Block Statement
• Generate Statement
• Configuration Specification
• Configuration Declaration

59
Basic Features

• Structural description of a piece of hardware is
  a description of what its sub-components are and
  how the sub-components are connected
• Structural description is more concrete than
  behavioral description. i.e. correspondence
  between a given portion of description and a
  portion of hardware is easier to see in
  structural descriptions
• Component Instantiation statement is basic unit
  of structural Description.
• Component instantiation can be done by -
• Instantiating a declared component and providing
  binding information to bind it with
  actual entity(architecture)
• Directly instantiating an entity(architecture).
  No separate component declaration and
  binding information is needed. ( VHDL
  93 feature)

60
Component Instantiation

• Component Instantiation statement specifies an
  instance of a component (child component)
  occurring inside another component (parent
  component)
• At the point of instantiation, only the external
  view of the child component (the names, types and
  directions of ports) is visible
• The statement identifies the child component and
  specifies the connectivity of the local signals
  or ports of parent component with the ports of
  child component
• General Form of the statement
• label instantiated_unit generic map
  association-list
• port map
  association-list
• instantiated_unit component component_name
• entity entity_name (architecture_iden
  tifier)
• configuration configuration_name

61
Component Instantiation

• Generic/Port map associations are omitted if the
  corresponding component declaration lacks
  generics/ports
• The component_name must reference a component
  declared by a component declaration. The
  component declaration need not occur in the
  architecture body containing the instantiation
  but it must be visible at the point of
  instantiation. (e.g through a visible package)
• A port of Component Declaration is called a local
• In a component instantiation statement, the port
  association list associates an actual with a
  local
• The associated actual must be
• an object of class signal
• open
• static expression if port mode is in

62
Example

• architecture Parent_body of Parent is
• component And2 -- Component Declaration
• port ( I1, I2 Bit O1 out Bit)
• end component
• signal S1, S2, S3 Bit
• begin
• Child And2 port map ( I1gtS1, I2gtS2,
  O1gtS3) -- Instance
• end Parent_body

63
Entity Vs Component

• ENTITY
• Entity is a library unit which can be compiled
  separately and it never occurs inside another
  library unit
• Entity declaration declares something that really
  exists in the design library

• COMPONENT
• Component Decl only occurs inside a library unit.
  It may occur
• inside a Package Decl or an architecture body
• Component declaration merely declares a template
  that
• does not exist in the design library

64
Port Association

• VHDL imposes three kinds of restrictions based on
  type mode and resolvability, on the association
  of an actual with local
• VHDL requires that the type of actual be the same
  as the type of the local
• VHDL requires that if the local is readable, then
  the actual must also be readable, and if the
  local is writable, then the actual must also be
  writable
• Association with a local of mode out or inout
  creates a source for the actual. It follows that
  an actual, which is not a resolved signal, may
  not be associated with more than one locals of
  mode out or inout

65
Example

• entity Invert_8 is
• port ( Inputs in Bit_vector (1 to 8)
• Outputs out Bit_vector (1 to 8))
• end Invert_8
• architecture Invert_8 of Invert_8 is
• component Inverter
• port ( I1 Bit O1 out Bit)
• end component
• begin
• G for I in 1 to 8 generate
• inv Inverter port map (Inputs(I),
  Outputs(I))
• end generate
• end Invert_8

66
Generics

• Generics provide a channel for static information
  to be communicated to a design-block from its
  environment.
• Typical use of generics are to parameterize
  timing, the range of subtypes, the number of
  instantiated sub-components, and the size of
  array objects (in particular the size of ports)
• Generics are declared as interface elements.
• The only object type permitted is constant.
• The only mode permitted is in.
• Allowed inside
• Entity Declarations
• Component Declarations
• Blocks

67
Example

• entity and_gate is
• generic (eg integer)
• port (eI1, eI2 in bit_vector(1 to
  eg) eO out bit_vector(1 to eg))
• end
• architecture and_gate_arch of and_gate is
• begin --- implementation not shown
• end
• entity top is end
• architecture top of top is
• signal s1, s2, s3 bit_vector(1 to 3)
• component gate
• generic (cg integer)
• port (cI1, cI2 in bit_vector(1 to
  cg) cO out bit_vector(1 to cg))
• end component
• for all gate use entity work.and_gate(and_ga
  te_arch)
• generic map (eg gt cg) port
  map (eI1 gt cI1, eI2 gt cI2, eO gt cO)
• begin
• AND1 gate generic map (cg gt 3) port
  map (cI1 gt s1, cI2 gt s2, cO gt s3)

68
Block Statement

• A block statement defines an internal block
  representing a portion of a design. Blocks may be
  hierarchically nested to support design
  decomposition
• A block may have three parts -
• block header, block declarative part, block
  statement part
• Block Header
• Block header explicitly identifies certain
  values, signals which are to be imported from
  the enclosing environment into the block and
  associated with formal generics and ports
• Block Declarative Part
• Type, subtype, subprogram, constant, signal
  etc can be declared in the block declarative
  part. These items are local to block scope.
• Block Statement Part
• Block statement part consists a set of
  concurrent statements.

69
Example

• entity ent is
• end
• architecture arc of ent is
• signal sig_a integer
• constant con_a time 1 ns
• begin
• B block
• --- block header part
• generic (bg time) generic
  map (bg gt con_a)
• port (bp1 in integer) port map
  (bp1 gt sig_a)
• --- block declarative part
• signal sig_b integer
• begin
• --- block statement part
• sig_b lt sig_a after bg
• end block
• end

70
Generate Statements

• A generate statement provides a mechanism for
  iterative or conditional elaboration of a portion
  of description
• Consists of a generation-scheme and a set of
  enclosed concurrent statements
• Following VHDL concurrent statements may be
  enclosed by the generate statement
• Process statement
• Block Statement
• Concurrent assertion statement
• concurrent signal assignment
• concurrent procedure call
• concurrent instantiation statement
• another generate statement

71
Generate Statements (contd.)

• General Form is
• label-identifier generation-scheme generate
• concurrent-statements
• end generate identifier
• There are two kinds of generation scheme
• if-scheme
• for-scheme

72
Example

• entity Invert_8 is
• port ( Inputs in Bit_vector (1 to 8)
• Outputs out Bit_vector (1 to 8))
• end Invert_8
• architecture Invert_8 of Invert_8 is
• component Inverter
• port ( I1 Bit O1 out Bit)
• end component
• begin
• G for I in 1 to 8 generate
• inv Inverter port map (Inputs(I),
  Outputs(I))
• end generate
• end Invert_8

73
Configuration Specification

• This construct allows the designer to specify the
  selection of entity declaration and architecture
  body for each component instance.
• General Form is
• for component_specification use
  binding_indication
• component_specification
• Identifies which instances are configured
• Consists of an instantiation label (or a label
  list) followed by colon and the component name
• binding_indication
• Specifies mapping between the component and the
  entity
• It may also contain a generic/port association
  list

74
Configuration Specification

• Example
• for U1, U2 Inverter use entity
  work.Inv1(Inv1_body)
• for all And_gate use entity work.And_gate1(And_g
  ate1)
• for others Inverter use entity
  work.Inv2(Inv2_body)
• Instantiation label allows two key words all and
  others
• Use of all means that the configuration
  specification applies to all the instantiations
  of the given component.
• Use of others means that the configuration
  specification applies to all the instantiations
  of the given component except for those instances
  which are already configured by the preceding
  configuration specifications

75
Configuration Declaration

• Configures sub-component hierarchy.
• The binding of a component instance to design
  entities can be performed by configuration
  specification which appears in the declarative
  part of the design-block in which the the
  corresponding component instance resides.
  Otherwise, the user can defer the binding of the
  component instance until later, leaving the
  component in the design-block unbound.
  Configuration declaration provides the mechanism
  for specifying such deferred binding.
• This has following two benefits
• Provides support for top-down design methodology
• Allows a designer to take advantage of a library
  of reusable components.

76
Example

• Consider the configuration declaration for an
  entity COMM_BOARD that fits into a full PC slot
• configuration FULL_SLOT of COMM_BOARD is
• for ARCH_COMM_BOARD
• for CPU PROCESSOR
• use entity std_parts.SPARC(intel)
  generic map (Clock gt 40 ns)
• for intel
• --- component configuration for
  instantiations in intel
• end for --- for intel
• end for --- for PROCESSOR
• --- configuration of other
  different units
• end for --- for architecture
  ARCH_COMM_BOARD
• end FULL_SLOT

77
Behavioral Description

• Sequential vs Concurrent
• Process Statement
• Wait Statement
• Behavioral Modeling - Sequential View
• Signal Assignment
• Delay in Signal Assignments
• Variable Assignment
• Sequential Statements
• Conditional Control
• Iterative Control
• Assertion Statement

78
Behavioral Description (contd.)

• Behavioral Modeling - Concurrent View
• Concurrent Signal Assignment
• Conditional Signal Assignment
• Selected Signal Assignment
• Resolved Signals

79
Sequential vs Concurrent

• In VHDL there are two levels at which designer
  must define the behavior of a discrete system
  sequential and concurrent level.
• The sequential level involves programming the
  behavior of each process that will be used in the
  model. Sequential statements are executed in the
  order in which they appear. Used for algorithmic
  descriptions.
• A concurrent statement executes asynchronously,
  with no defined relative order. Concurrent
  statements are used for data-flow and structural
  descriptions
• The process statement is a concurrent statement
  which delineates set of sequential statements.
  Process statements are executed concurrently but
  the statements inside a process statement are
  executed sequentially.

80
Process Statement

• The process statement is a concurrent statement
  that defines a specific behavior to be executed
  when the process becomes active. The behavior of
  the process is described with a set of sequential
  statements.
• General Form is
• process_label
• process
• declarations
• begin
• statements
• end process

81
Process Statement (Contd.)

• A process is either active or suspended
• A process becomes active when any of the signal
  read by the process changes its value
• All active processes are executed concurrently
• A process may be suspended upon execution of a
  wait statement in the process. The process
  remains suspended until its reactivation
  condition is met

82
Wait Statement

• Three kind of reactivation condition can be
  specified in a wait statement
• timeout wait for
  time-expression
• condition wait until
  condition
• signal sensitivity wait on signal-list
• Conditions can be mixed. e.g
• wait on A, B until Enable 1
• If a process is always sensitive to one set of
  signals, it is possible to designate sensitivity
  signals using a sensitivity list.
• It is illegal to use wait statement in a process
  with a sensitivity list
• Every process is executed once upon
  initialization

83
Example

• The following process implements a simple OR
  gate--
• --- this process is sensitive to signals In1 and
  In2
• Or_process process (In1, In2)
• begin
• Output lt In1 or In2
• end process
• --- this is equivalent to
• Or_process process
• begin
• Output lt In1 or In2
• wait on In1, In2
• end process

84
Sequential Assignment

• This assignment occurs in a process or subprogram
• It is sequentially executed
• There are two fundamental types of assignment
• Signal Assignment
• Variable assignment

85
Signal Assignment

• A signal is comprised of a current value and a
  projected waveform
• The current value always holds the value of the
  signals as read by other process
• The projected waveform contains scheduled values
  on this signal at future times
• Simplest form
• signal_name lt value
• This assigns value to the current value of the
  signal at the beginning of the next cycle

86
Signal Assignment (contd.)

• Delay in signal assignment
• It is possible to assign values with a delay
• Delay is relative to current time
• If no explicit delay is specified a delta delay
  is assumed
• General Form
• signal_value lt value after time-expression

87
Example

• Consider this Example
• signal A Bit 0
• signal B Bit 1
• P1 process
• begin
• B lt A
• assert ( B A) report B is not equal to A
  severity error
• wait on B
• end process
• Will the message be printed ?

88
Signal Drivers

• A driver is a collection of value time pairs
  referred to as transactions
• Every concurrent statement which assigns to a
  signal creates a driver for that signal
• Only one driver is allowed for a signal unless it
  is a resolved signal
• Initial value of the driver is taken from the
  default value of the declaration which is visible
  to the source process. If source process is in
  another component it is taken from the port .

89
Delay in Signal Assignment

• There are two types of delay that can be applied
  when assigning a time/value pair into the driver
  of a signal
• Inertial Delay
• Transport Delay

90
Inertial Delay

• Inertial delay models the delays often found in
  switching circuits. An input value must remain
  stable for a specified time (pulse rejection
  limit) before the value is allowed to propagate
  to the output.
• The value appears at the output after the
  specified inertial-delay.
• If the input is not stable for specified
  rejection limit (pulse rejection limit), no
  output change occurs.
• Inertial signal assignment has the form
• signal_object lt reject
  pulse-rejection-limit inertial
• 
  expression after inertial-delay-value
• Example
• Z lt reject 4 ns inertial A after 10ns

91
Transport Delay

• This delay models pure propagation delay ie, any
  change in the input (no matter how small) is
  transported to the output after the specified
  delay time period
• To use a transport delay model, the keyword
  transport must be used in a signal assignment
  statement
• Ideal delay modeling can be obtained by using
  this delay model, where spikes would be
  propagated through instead of being ignored

92
Variable Assignment

• A variable is declared in a process or a
  subprogram
• When a variable is declared with a process it
  retains its value throughout the simulation. i.e
  it is never re-initialized
• Variables declared in subprograms are
  reinitialized whenever the subprogram is called
• General Form of variable assignment is
• variable_name expression
• The variable assignment updates the value
  immediately after the assignment without any
  delay

93
Conditional Control

• These sequential statements provide conditional
  control i.e statements are executed when a given
  condition is true
• VHDL provides two types of conditional control
  statements
• if then elsif
• case end case

94
If Statement

• General form is
• if condition then
• statement
• elsif condition then
• statement
• else
• statement
• end if

95
Example

• And_process process
• begin
• if In1 0 or In2 0 then
• Out lt 0 after Delay
• elsif In1 X or In2 X then
• Out lt X after Delay
• else
• Out lt 1 after Delay
• end if
• wait on In1, In2
• end process

96
Case Statement

• General Form is
• case expression is
• when value gt
• statements
• when value value gt
• statements
• when discrete_range gt
• statements
• when others gt
• statements
• end case

97
Example

• Select_process process
• begin
• case X is
• when 1 gt Out lt 0
• when 2 3 gt Out lt 1
• when others gt
• out lt X
• end case
• end process

98
Iterative Control

• In this control the execution iterates over the
  statements until some condition is met
• VHDL provides iterative control inform three
  kinds of loop statements
• Simple loop
• for loop
• while loop

99
Simple Loop

• Simple loop encloses a set of statements in a
  structure which is set to loop forever
• General Form is
• loop_label loop
• statements
• end loop loop_label

100
Example

• P1 process
• variable A Integer 0
• variable B Integer
• begin
• Loop1 loop
• A A 1
• B 20
• Loop2 loop
• B B - A
• end loop Loop2
• end loop Loop1
• wait
• end process

101
For Loop, While Loop

• General Form of for loop
• loop_label
• for loop_variable in range loop
• statements
• end loop loop_label
• General Form of while loop
• loop_label
• while condition loop
• statements
• end loop loop_label

102
Example

• P1 process
• variable B Integer 1
• begin
• Loop1
• for A in 1 to 10 loop
• B 20
• Loop2
• while B gt (A A) loop
• B B - A
• end loop Loop2
• end loop Loop1
• wait
• end process

103
Exit Statement

• Exit statement is a sequential statement closely
  associated with loops and causes the loop to be
  exited
• Exit statement has two general forms
• exit loop_label
• exit loop_label when condition
• P1 process
• variable A, B Integer 0
• begin
• Loop1 loop
• A A 1
• B 20
• exit Loop1 when A 20
• end loop Loop1
• end process

104
Next Statement

• Next statement is used to advance control to the
  next iteration of the loop
• General Form is next loop_label when condition
• Example
• for j in 1 to 10 loop
• if var1 var2 then
• next
• elsif var1 lt var2
• var1 var1 1
• else
• null
• end if
• k k 1
• end loop

When next statement is executed, execution jumps
to the end of the loop, i.e last statement k
k 1, is not executed. Loop identifier j
increments and then loop execution resumes with
new value of j.
105
Assertion Statement

• The assertion statement has the syntax
• assert condition report message severity level
• When the condition is FALSE the message is sent
  to system output with an indication of the
  severity of the message
• The severity levels are Note, Warning, Error and
  Failure
• If no message is given the default message is
  Assertion Violation. The default level is Error
• Example
• assert (A B)
• report A is not equal to B
• severity Error

106
Concurrent Signal Assignment

• A concurrent signal assignment statement
  represents an equivalent process that assigns
  values to signals
• Simple example of concurrent signal assignment is
  target_sig lt source_sig after delay_period
• It is one of the primary mechanisms for modeling
  the data-flow behavior of an entity
• There are two forms of concurrent signal
  assignment
• 1) conditional signal assignment
• 2) selected signal assignment

107
Example

• architecture arch_sub of sub is
• begin
• process (in1, in2)
• begin
• Out1 lt In1 - In2 after Delay
• end process
• end arch_sub

108
Conditional Signal Assignment

• This is a special form of concurrent signal
  assignment. Signal Assignment is done when
  condition is true.
• General Form is
• target lt options
• waveform1 when condition1 else
• .
• .
• waveformN-1 when conditionN-1 else
• waveformN
• The behavior is similar to that of an if
  statement in a process statement

109
Example

• architecture Conditional of AND_gate is
• begin
• Y lt transport
• 1 after Delay when A1 and B1 else
• 0 after Delay
• end Conditional

architecture ConditionalEq of AND_gate
is begin process(A,B) begin if A1 and B1
then Y lt transport 1 after Delay else Y
lt transport 0 after Delay end process end
ConditionalEq
110
Selected Signal Assignment

• Selected Signal Assignment behaves very much like
  the case statement in a process statement
• General Form is
• with expression select
• target lt options
• waveform1 when choices1,
• .
• .
• waveformN when choicesN

111
Complete Example

• Example 1 -- A Package with a procedure modeling
  the functionality of an OR gate
• package gate is
• procedure Or_gate(signal In1, In2 bit signal
  Out1 out bit)
• end gate
• package body gate is
• procedure Or_gate(signal In1, In2 bit signal
  Out1 out bit) is
• begin
• Out1 lt In1 or