Formalizing and Enhancing Verilog

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Formalizing and Enhancing Verilog

• Presenter Cherif Salama
• Jennifer Gillenwater, Gregory Malecha,
• Angela Yun Zhu and Walid Taha
• Rice University
• Jim Grundy and John OLeary
• Intel Strategic CAD Labs

Research ID 1403 RIDL-V
A Resource-Aware Programming (RAP) Extension of
Verilog
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Problem Description

• VHDL and Verilog have useful abstractions like
  iterations and parameterized modules
• Elaboration replaces abstractions with specific
  hardware descriptions
• Synthesizability of hardware descriptions cannot
  be determined statically before elaboration
• Thus, hardware designers avoid abstractions,
  which makes written designs longer and less
  generic

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Goal

• Statically verify synthesizability of hardware
  descriptions without sacrificing the ability to
  use higher level abstractions

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Ripple Adder Example
module adder(s,cout,a,b,cin) parameter N4
input N-10 a,b input cin output
N-10 s output cout wire N0 c
genvar i assign c0 cin for(i0
iltN ii1) full_adder fa
(si,ci1,ai,bi,ci) assign cout
cN endmodule
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Can Synthesizability be Determined Statically?

• Proposed Method
• Use Statically Typed Two-level Languages (STTL)
• Preprocessing is level 0 computation
• The remaining computation is level 1
• Formalize
• Syntax
• Type System
• Preprocessing Semantics

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Formalization - Syntax

• Featherweight SystemVerilog (FSV) A calculus for
  a representative core of Verilog
• All constructs except parameterized modules and
  for-loops are trivially synthesizable, as they
  have straightforward hardware equivalents
• Formalization done using Backus-Naur Form (BNF)

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Formalization - Preprocessing Semantics

• Formalize the elaboration phase
• Substitute parameters with their actual values
• Evaluate expressions
• Passed as parameter values when instantiating
  modules
• Controlling for-loops iterations
• Used as indices, ranges, or delays
• Create a specialized module each time a module is
  instantiated with different parameter values
• Unroll for-loops
• Formalization done using Big Step Operational
  Semantics

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Preprocessing Example
module adder_2(s,cout,a,b,cin) ...
full_adder fa_0 (s0,c1,a0,b0,c0)
full_adder fa_1 (s1,c2,a1,b1,c1)
... endmodule module adder_4(s, cout, a, b,
cin) input 30 a,b input cin
output 30 s output cout wire 40 c
integer i assign c0 cin full_adder
fa_2 (s0,c1,a0,b0,c0) full_adder
fa_3 (s1,c2,a1,b1,c1) full_adder
fa_4 (s2,c3,a2,b2,c2) full_adder
fa_5 (s3,c4,a3,b3,c3) assign cout
c4 endmodule module main() ...
adder_2 d1_0 (s1,cout1,a1,b1,cin1) adder_4
d2_0 (s2,cout2,a2,b2,cin2) ... endmodule
module adder(s,cout,a,b,cin) parameter N4
input N-10 a,b input cin output
N-10 s output cout wire N0 c
genvar i assign c0 cin for(i0
iltN ii1) full_adder fa
(si,ci1,ai,bi,ci) assign cout
cN endmodule module main() ... adder
(2) d1 (s1,cout1,a1,b1,cin1) adder (4) d2
(s2,cout2,a2,b2,cin2) ... endmodule
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Formalization - Type System

• Verify that the correct signal types and
  directions are used
• Verify that expressions that need to be evaluated
  during preprocessing do not depend on wire value
• Formalization done using two-level typing rules

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Results

• By formalizing FSV as an STTL we proved
• Type Safety Preprocessing of a well-typed
  description does not produce an error
• Type Preservation Preprocessing of a well-typed
  description produces a well-typed description
• Preprocessing Soundness Preprocessing Produces a
  description that is free from abstractions
• In FSV, a description is synthesizable because it
  is well-typed and abstraction-free

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Implementation

• No preprocessing errors

• Well-Typed
• Abstraction-Free
• Synthesizable

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Are Abstractions Valuable in Practice?

• Using abstractions, we manually re-factored some
  practical examples

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Conclusion

• Treating Verilog as an STTL, we could
• Formalize elaboration
• Statically check for synthesizability using
  typing rules
• Safely use abstractions leading to better designs
  without compromising synthesizability

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Future Work

• Write various circuits using abstractions and
  compare the quality of the generated description
  with industrial strength circuits
• Use the same framework to statically provide
  other guarantees about the hardware descriptions
  including matching bus sizes, area, timing, and
  power

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Thank You !