Recent Research Progresses in Zhejiang University

1
Recent Research Progresses in Zhejiang University

• Xiaolang Yan

2
Outline

• Introduction
• Design For Manufacture
• Formal Verification
• SoC and Platform Design

3
Introduction

• Recent RD Activities
• Research in the ICSOC framework
• Research supported by various funding
• RD in joint labs with Samsung and National
  Semiconductor
• Industrial co-operations
• Recent Educational Activities
• A series of short courses given by 8 professors
  from U.S., in IC training center in Hangzhou
• Joint master and Ph.D. programs with Royal
  Institute of Technology, Sweden (KTH)

4
Design For Manufacture

• Lithographic Modeling
• New OPC Methods
• Full-Chip PSM Processing Tool
• Manufacturing Pattern Verification
• DFM of Standard Cells
• New Processes Development

5
Lithographic Modeling

• New Test Structure Generation Tool
• Script-driven automatic layout generation
• Testing for various physical settings
• Prepared for fine model characterization
• 130nm, 90nm Lithographic Model Fitting
• Well-matched results with measurements obtained

6
Content-Driven OPC Method

• Content-Driven Dissection and Correction
• Processing emphasis is put on functional parts
  such as channels
• New Dissection Method for Frugal OPC
• Distortion is measured as one criterion for edge
  dissection

7
Full-chip PSM processing

• Phase Shifter Insertion and Phase Assignment on
  Full Chip Level
• Red/Blue phase shifter with 0/180 phases

8
Sub-100nm Standard Cell Designs

• Sub-100nm Standard Cell DFM Flow and Real Design
  Cases
• Trial OPC, trial PSM steps are added in the
  design flow
• Lithographic simulation is performed to analyze
  the manufacturability of designed cells in
  different environment settings
• Cells are being verified in test circuitries on
  test chips.
• A 90nm DFF designed with good
  manufacturability

9
Test patterns zoomed-in
2D Patterns
1D Patterns
SARFs



10
Cells and testing circuitries
8 bit Counter
8 bit Adder
11
Tape-out
12
Formal Verification

• Verification-Oriented Synthesis
• Combinational Equivalence Checking
• Sequential Equivalence Checking with Retimed
  Circuits
• Integrated Arithmetic Verification Based on
  Abstraction Refinement

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Combinational / Sequential EC

• Using CEC to Verify Sequential Design
• New Algorithms for Retimed Circuit are in
  Researching

14
Arithmetic Verification

• Arithmetic Verification Based on Abstraction
  Refinement
• To translate Verilog to abstract-level languages
  such as CLU, SVC
• Datapath abstraction methods
• Modeling the Datapath Element by,
• ILP constraints
• Presburger arithmetic
• New Hybrid Approaches in CLU Can Be Verified in
  UCLID(from CMU)

15
SoC and Platform Design

• Embedded CPU Design and Its Development Platform
• CPU core design
• MCU and core-centric applications design
• Co-design platform and full software development
  platform
• New DSP Core Design
• CPU DSP structure
• Development platformsFPGA

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32-bit embedded CPU

• 7 Pipeline Stages
• High Instruction Density
• Real-Time Response Scheme
• CK520 Enhanced Version
• Hi-speed I-cache/D-cache
• Memory protection
• 64 bit DSP instruction
• Freq. 250MHz

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• Thank you!