Design Tools for Networked SystemonChip

1
Design Tools for Networked System-on-Chip

• Rajesh K. Gupta
• Center for Embedded Computer Systems
• University of California, Irvine
• Irvine, CA 92612
• gupta_at_uci.edu

2
Outline

• Design tools for networked system-on-chip
• Design technology challenges in networked SOCs
• Two views of Networked SOCs
• compositional (or ASIC view)
• architectural (or network-centric view)
• Scope and categories of design tools for NSOCs
• System-level composition through OO mechanisms
• Network architectural modeling
• Implementation tools
• RF circuit design tools
• accurate device modeling circuit simulation
• antennae design and EM simulation tools
• Summary

3
System-Chips

• A system consists of parts
• that are designed independently, and often
  without knowledge of their eventual
  application(s)
• System-on-Chip
• a system built from pre-designed parts
• enormous challenges since pre-designed silicon
  parts do not compose well across multiple design
  data representation
• testing methods and ensuring testability is even
  harder
• SOCs in networking and wireless applications
• face unique design and design technology
  challenges due to component heterogeneity.

4
Design Technology Challenges in Networked SOCs

• Inferior CMOS components compared to discrete
  counter-parts using bipolar and GaAs technologies
• Power, size, bandwidth limitations for on-chip
  processing
• An extremely tight control of chip, package
  parasitic RF paths is needed for on-chip RF
  transceivers
• And yet the system-level performance can be
  higher due to
• architectural design that is less sensitive to
  device/technology limitations/variations
• the ability to integrate passive devices,
  sophisticated signal processing and even digital
  computations to adapt to application,
  environment and even device/technology
  characteristics.
• This requires ability to carry out rapid
  architectural and design space explorations.

5
How will we design these system-chips?

• There are two distinct views of NSOC
• Compositional or ASIC view
• SOC design is a ultimately an integrated circuit
  design
• demands from mother-nature must be met.
• Network centric view
• Protocol and communication functions are central
  to chip functionality
• The really hard part is figuring out how to
  relate sub-system performance enhancements to
  end-user performance.
• I find the hardest part to be making trade-offs
  so as to optimize across the various layers
  (physical, link, network, transport, application)
  of the communication system. We need tools and
  techniques to co-design these layers, instead of
  separate black-box optimizations.
• Regardless of the view, one fact is abundantly
  clear that
• IC Designer is also a networked systems designer.

6
Compositional View ASIC
7
Network Systems View
8
ASIC Network Models

• Complementary models
• ASIC models focus on node implementation
• Network model keeps multi-node system view
• Example Synopsys Protocol Compiler, NS models.
• Theoretically both models can support either
  view
• Designers often need the ability
• to tradeoff across layers (easier in ASIC models)
  while
• keeping the system view (easier in network
  models).
• Hence, a convergence in works on integration of
  ASIC and Network models
• MIL3 OPNET, Cadence Bones, Diablo
• HP EEsofs ADS, AnSoft HFSS, Cadence Allegro,
  Anadigics, White Eagle DSP, ...

9
Scope of NSOC Design Tools

• Design of single-chip systems with radio
  transceivers requires tools
• to explore new architectures containing
  heterogeneous elements
• to explore circuit design containing
  analog/digital, active/passive components (mixed
  signal design)
• to accurately estimate parasitic effects, package
  effects
• Typically mixed-system design entails
• antennae design
• network design interference, user mobility,
  access to shared resources
• algorithmic simulations
• protocol design
• circuit design, layout and estimation tools

10
Categories of Design Tools

• Architectural design tools
• network, protocol simulations
• algorithmic simulations, partitioning and mapping
  tools
• Design environment tools
• encapsulated libraries, library management for
  design components
• Module design
• low noise integrated frequency synthesizers
• base-band over-sampled data converters
• design of RF, analog, digital VLSI modules
• Modeling, characterization and validation tools
• characterization of mixed-mode designs, RF
  coupling paths, EMI
• simultaneous modeling, design and optimization of
  antenna, passive RF filter, RF amp, RF receiver,
  power amp. components

11
System Design
Traditional Design Process
Simulation and Synthesis Based Design Process
Courtesy HP

• Integrated simulation and synthesis capabilities
  are key to SOC designs
• Goal is to quickly and accurately analyze system
  performance
• Top-level system brainstorming
• Quick analysis of circuit interactions
• Budget analysis to allocate circuit
  specifications
• Design partitioning

12
Compositional View to NSOCs

• Design methodology for system-chips derived from
  ASIC design methodologies
• ASIC methodologies evolving into
• Block-based Designs (BBD)
• core components modeled at behavioral/RTL level
• Platform-based Designs (PBD)
• architectural design using virtual components
• relies on interface standards and reference
  architectures.

13
Platform-based methodology

• Platform based design
• Application mapped on architecture
• Performance evaluation and iterative refinement
• Challenges
• complete system simulation
• complexity management
• composability and reuse
• Key elements for composability
• Identification and use of useful models of
  computation
• FSMD, DE, DF, CSP, ...
• A flexible, extensible language platform to
  capture the functionality.
• Composability can be achieved using
  Object-oriented mechanisms
• UCI Balboa project http//www.cecs.uci.edu/balbo
  a

14
Composability in Balboa

• Large design composed of small behavioral blocks
• Design duality
• Functional model describe and synthesize
• Structural model capture and simulate
• Object mechanisms enables you to compose
  structural with functional information at the
  highest levels of abstraction

15
Structural information through object
relationships

• Object oriented design philosophy
• mapping of a physical object structure onto a
  conceptual object structure
• Structural information should be expressed in two
  way
• class diagram for the abstract view
• sets of classes and relationships
• object diagram for the concrete view
• netlist of entities communicating through signals
• We can define and use object patterns at every
  layer of abstraction

16
Object compositions through relationships FSMD
example
17
Different levels of abstraction

• Patterns set of extensible reoccurring design
  problems with known solutions
• IP identification
• Object patterns at each level of abstraction for
• models of computation
• process networks, fsmd, etc.
• components
• bus, signal, memory, cpu, logic block, ALUs,
  registers, latches, muxes, etc.

18
Different levels of abstraction (2)
19
Physical properties
20
The processor pattern
21
The bus-protocol pattern
22
Methodology

• Step 1 Identify the model of computation
• write an early model of the specification with
  it, use semantics to capture it formally
• Step 2 Identify the model of the architecture
• define and allocate design units
• Step 3 Distribute functionality on the
  structure
• bind MoC to design units
• distribute functionality across the structure
  with polymorphism
• Step 4 Iterative refinement by object
  decomposition
• compose a big object with smaller objects
  (through patterns)
• have smaller MoC and a growing number of smaller
  components

23
The UCI Balboa Project

• Design expressed in terms of objects and
  relationships
• Object patterns for each level of abstraction
• Abstract semantic used to store the object, to be
  able to use different simulator and synthesizer

24
Network Architectural Design

• or behavioral design for wireless systems
• Design network architecture
• point-to-point, cellular, etc
• Design protocols
• specification
• verification at various levels link, MAC,
  physical
• Tools in this category
• Matlab, Ptolemy (and likes)
• network, protocol simulators
• Tools are designed for simulations specific to a
  design layer
• simulation tools for algorithm development
• simulation tools for network protocols
• simulation tools for circuit design, hardware
  implementation, etc.

25
Network Architecture Modeling NS

• Developed under the Virtual Internet Testbed
  (VINT) project (UCB, LBL, USC/ISI, Xerox PARC)
• Captures network nodes, topology and provides
  efficient event driven simulations with a number
  of schedulers
• Interpreted interface for
• network configuration, simulation setup
• using existing simulation kernel objects such as
  predefined network links
• Simulation model in C for
• packet processing
• changing models of existing simulation kernel
  classes, e.g., using a special queuing
  discipline.

26
Example A 4-node system with 2 agents, a
traffic generator

• Agents are network endpoints where
  network-layer packets are constructed or consumed.

n0 UDP
set ns new Simulator set f open out.tr w ns
trace-all f set n0 ns node set n1 ns
node set n2 ns node set n3 ns node ns
duplex-link no n2 5Mb 2ms DropTail ns
duplex-link n1 n2 5Mb 2ms DropTail ns
duplex-link n2 n3 1.5Mb 10ms DropTail set udp0
newagent/UDP ns attach-agent n0 udp0 set
cbr0 newapplication/Traffic/CBR cbr0
attach-agent udp0 .. ns at 3.0 finish proc
finish () ns run
n2
n3 Sink
n1 TCP
ftp
27
NS v2 Implementation and Use

• A Split-level simulator consisting of
• C compiled simulation engine
• Object Tcl (Otcl) interpreted front end
• Two class hierarchies (compiled, interpreted)
  with 1-1 correspondence between the classes
• C compiled class hierarchy
• allows detailed simulations of protocols that
  need use of a complete systems programming
  language to efficiently manipulate bytes, packet
  headers, algorithms over large and complex data
  types
• runtime simulation speed
• Otcl interpreted class hierarchy
• to manage multiple simulation splits
• important to be able to change the model and
  rerun
• NS pulls off this trick by providing tclclass
  that provides access to objects in both
  hierarchies.

28
NS Implementation

• Example
• Otcl objects that assemble, delay, queue.
• Most routing is done in Otcl
• HTTP simulations with flow started in Otcl but
  packet processing is done in C
• Passing results to and from the interpreter
• The interpreter after invoking C expects
  results back in a private variable tcl_-gtresult
• When C invokes Otcl the interpreter returns the
  result in tcl_-gtresult
• Building simulation
• Tclclass provides simulator with scripts to
  create an instance of this class and calling
  methods to create nodes, topologies etc.
• Results in an event-driven simulator with 4
  separate schedulers FIFO (list) heap calendar
  queue real-time.
• Single threaded, no event preemption.

29
NS Usage LAN nodes

• LAN and wireless links are inherently different
  from PTP links due to sharing and contention
  properties of LANs
• a network consisting of PTP links alone can not
  capture LAN contention properties
• a special node is provided to specify LANs
• LanNode captures functionality of three lowest
  layers in the protocol stack, namely link, MAC
  and physical layers.
• Specifies objects to be created for LL, INTF, MAC
  and Physical channels.
• Example
• ns make-lan ltnodelistgt ltbwgt ltdelaygt ltLLgt ltifqgt
  ltMACgt ltchannelgt ltphygt
• ns make-lan n1 n2 bw delay LL
  queue/DropTail Mac/CSMA/CD.
• Creates a LAN with basic link-layer, drop-tail
  queue and CSMA/CD medium access control.

The LAN node collects all the objects shared on
the LAN.
n1
n2
n1
n2
LAN
n3
n3
30
Network Stack simulation for LAN nodes in ns
Objects used in LAN nodes. Each of the underlying
classes can be specialized for a given simulation.
Channel object simulates the shared medium and
supports the medium access mechanisms of the MAC
objects on the sending side.
On the receiving side, MAC classifier is
responsible for delivering and optionally
replicating packets to the receiving MAC objects.
31
Modeling of Mobile Nodes

• From CMU Monarch Group
• Allows simulation of multihop ad hoc networks,
  wireless LANs etc.
• Basic model is a MobileNode, a split object
  specialized from ns class Node
• allows creation of the network stack to allow
  channel access in MobileNode
• A mobile node is not connected through Links
  to other nodes
• Instead, a MobileNode includes the following
  mobility features
• node movement (two dimensional only)
• periodic position updates
• maintaining topology boundary

32
Mobile Nodes

• As in wireline, the network plumbing is
  scripted in Otcl
• Four different routing protocols (or routing
  agents) are available
• destination sequence distance vector (DSDV)
• dynamic source routing (DSR)
• Temporally ordered routing algorithm (TORA)
• Adhoc on-demand distance vector (AODV)
• A mobile node creation results in
• a mobile node with a specified routing agent, and
  
• creation of a network stack consisting of
• LL (with ARP), INT Q, MAC, Network Interface with
  an antenna.
• Enables integrated event driven simulation of
  mixed networks.

33
Mobile Node

• Node/MobileNode instproc add-interface channel
  pmodel lltype mactype qtype qlen iftype anttype
  
• self instvar arptable_ nifs_
• self instvar netif_ mac_ ifq_ ll_
• set t nifs_
• set netif_(t) new iftype net-interface
• set mac_(t) new mactype mac layer
• set ifq_(t) new qtype interface queue
• set ll_(t) new lltype link layer
• set ant_(t) new anttype
• ..
• set topo topography
• topo bind_flatgrid opt(x) opt(y)
• node set x_ ltx1gt
• node set y_ lty1gt
• ..

34
Network Simulation using OPNET

• Commercially available from MIL3
• Heterogenous models
• for network
• for node
• for process
• Network, node, process editors
• Network models consist of node and link objects
• Nodes represent hardware, software subsystems
• processors, queues, traffic generators, RX, TX
• Process models represent protocols, algorithms
  etc
• using state-transition diagrams
• Simulation outputs typically include
• discrete event simulations, traces, first and
  second order statistics
• presented as time-series plots, histograms, prob.
  density, scattergrams etc.

35
OPNET Wireless System Modeling

• OPNET modeler with radio links and mobile nodes
• Mobile nodes include three-dimensional position
  attributes that can change dynamically as the
  simulation progresses.
• Node motion can be scripted (position history) or
  by a position control process.
• Links modeled using a 13-stage model where each
  stage is a function (in C)
• Transmitter stages
• Transmission delay model time required for
  transmission
• Link closure model determine reachable receivers
• Channel match model determine which RX channel
  can demodulate the signal (rest treat it as
  noise)
• Transmitter antenna gain computes gain of TX
  antenna in the direction of the receiver
• Propagation delay model time for propagation
  from TX to RX.

36
Link Model Stages

• Receiver stages
• RX antenna gain in the direction of the receiver
• Received power model avg. received power
• Background Noise Model computes the in-band
  background noise for a receiver channel
• Interference noise model typically total power
  of all concurrent in-band transmission
• SNR model SNR of transmission fragment based on
  the ratio of received power and interference
  noise
• BER model computes mean BER over each constant
  SNR fragment of the transmission
• Error Allocation Model determines the number of
  bit error in each fragment of the transmission
• Error Correction Model determines whether the
  allocated transmission errors can be corrected
  and if the transmitted data should be forwarded
  in the node for higher level processing.

37
Communications Toolbox (MATLAB)

• Part of the MATLAB DSP workshop suite
• functionality models from MATLAB
• sources, sinks and error analysis
• coding, modulation, multiple access blocks, etc.
• communication link models from SIMULINK
• channel models Rayleigh, Rician fading, noise
  models
• Good front-end simulations through vector
  processing
• handles data at different time-points in large
  vectors
• used in modeling physical layer component such as
  modems
• useful in algorithm development and performance
  analysis
• for modulation, coding, synchronization,
  equalization, filter design.

http//www.mathworks.com/products/communications/i
ndex.shtml
38
NSOC Simulation

• There are three classes of simulations
• 1. Data-flow or untimed simulations
• simulation of filters, receivers, DSP functions,
  
• 2. Clock-based simulations
• simulation of synchronous behaviors
• 3. Event-based simulations
• simulation of asynchronous behaviors
• Underlying semantics of many simulation-based
  tools can be classified along these three types.
• Within each type basic simulation mechanism is
  the same
• However, there are substantial differences in
  library support for simulation objects depending
  upon the simulation target
• protocol development
• algorithm design
• hardware design.

39
Co-Simulation

• Simulation of systems with mix of
• hardware, software components
• analog elements, digital elements
• Co-simulation can be done at either the modeling
  level or at the system implementation level
• modeling level using heterogeneous models such as
• imperative programs, finite state machines,
  process networks, discrete event components,
  data-flow blocks.
• implementation level consists of
• machine code, ASIC hardware, gate-level blocks,
  analog models.

40
Co-Simulation Difficulties

• Different system components run at different
  levels of abstraction (use different levels of
  data), run at different speeds and are triggered
  by different sets of events
• analog components operate over voltages and
  currents and time, digital logic operates over
  binary values, and microprocessors operate over
  instructions.
• a microprocessor may take one or more cycle to
  execute an instruction, during which time analog
  or digital devices may go through several changes
  of state.

41
Co-Simulation Coordination Across Domains

• Example PTOLEMY
• Unified simulation framework
• Particular model of computation referred to as a
  design style
• Domain as objects consisting of
• blocks (as a design style)
• operational semantics for blocks
• targets
• a scheduling discipline
• programming in C
• Example domains SDF, DE, Thor.
• Domains are powerful enough to model activities
  from antennae design to solving differential
  equations within a domain.

42
Available Co-Simulation Environments

• Ptolemy (UC Berkeley)
• EEsoft from HP targeted for RF designs
• MATLAB DSP Workshop
• SPW (Alta/Cadence)
• Mentor Graphics DSP workstation
• COSSAP (Synopsys)
• Hardware/software co-design tools
• Bones, Polis, Seamless, ...

43
Implementation Tools

• Functional mapping to system components
• system partitioning and mapping tools
• RF circuit design and entry tools
• Linear circuit simulation
• Nonlinear circuit simulations
• EM field simulations
• Performance verification tools
• Evaluation boards
• for individual RF ICs
• Motorolas RFIC demo boards
• Momenta Design System board
• channel emulator boards

44
RF Component Design Flow
Concept
Design
Production
Integration Test

• System Analysis
• Design Partitioning

• RF
• Analog
• DSP

• Integrate Blocks
• System Measurements
• Re-Layout

• Final Artwork
• Bill of Materials
• Documentation

• Layout
• EM Simulation
• Parts Libraries
• Third Party Links

• Co-Simulation
• System Simulation

• Artwork Generation

• Device models
• Circuit simulations

45
Circuit Simulators

• SPICE
• a time domain simulator
• time step chosen for the highest frequency
  component in the signal
• long runtimes
• can not handle frequency domain models
• Digitally modulated RF signals are narrow-band
  signals at high carrier frequencies
• Spectral decomposition is not sufficiently
  accurate for system performance analysis (e.g.,
  BER)

46
RFBB Circuit Simulations

• Four approaches
• Harmonic balance
• use decomposition of modulated signals
• steady state view of the system
• used in ADS
• Periodic steady state analysis
• used in SpectreRF
• Envelope transient analysis
• replace differential equations by algebraic
  equations
• waveform envelope computation with numerical
  integration
• while carrier signals are computed with Harmonic
  balance
• Block processing
• alternate between frequency and time domain
  through transformations

47
Mixed Signal Simulators

• AnalogDigital
• single kernel that combines both digital and
  analog simulations on a common backplane
• ATTSIM (Verilog, VHDL and SPICE, behavioral C
  code)
• Mentor Graphics QuickHDL Eldo (AnaCad) SPICE
• third party simulation backplane
• SimMatrix from Precedence
• RFBB
• EESofs Circuit Envelope
• handles signals amplitude and phase modulation
  information in time domain
• RF carriers and harmonics in frequency domain
  using s-parameter data instead of lumped models.
• Cadences SpectreRF

48
Putting It Together
49
Chip-level System Building Blocks
50
System-Chips

• A system consists of parts
• that are designed independently, and often
  without knowledge of their eventual
  application(s)
• System-on-Chip
• a system built from pre-designed parts
• enormous challenges since pre-designed silicon
  parts do not compose well across multiple design
  data representation
• testing methods and ensuring testability is even
  harder.
• Design methodology for system chips
• ASIC methodologies evolving into
• Block-based Designs (BBD)
• core components modeled at behavioral/RTL level
• Platform-based Designs (PBD)
• architectural design using virtual components
• relies on interface standards and reference
  architectures.

51
Managing Complexity Cores

• Cores a working definition
• at least 5K gates
• pre-designed and pre-verified
• re-usable as code, codenetlist, layout...
• Examples
• Wireless Spread-spectrum ICs (Sirius), ADC,
  DAC, PLLs, Transceiver circuit blocks.
• LSI logic CW4001/4010/4100, ARM 7TDMI, ARM 810,
  NEC 85x, Motorola 680x0, IBM PPC
• DSP cores TI TMS320C54X, Pine, Oak
• Encryption PKuP, DES
• Controllers USB, PCI, UART
• Multimedia JPEG comp., MPEG decoder, DAC
• Networking ATM SAR, Ethernet

52
Core Types

• Soft cores (code)
• HDL description
• flexible, i.e., can be changed to suit an
  application
• technology independent may be resynthesized
  across processes
• significant IP protection risks
• Firm cores (codestructure)
• gate-level netlist to be placed and routed
• technology sampled
• Hard cores (physical)
• ready for drop in
• include layout and timing (technology dependent)
• IP is easily protected
• mostly processors and memory
• functional test vectors or ATPG vectors available.

53
Core Types and Their Use
system specification
Bus Functional
Behavioral HDL
Soft
ISA model
scheduling, binding
system design
RTL HDL
RTL Functional
Synthesizable RTL
control generation, FSM synthesis
logic design
Gate Netlist
Gate Functional
Firm
floorplanning, placement, routing
Timing models
Power models
physical design
Fault Coverage
Mask Data
Hard
Technology ASIC or FPGA
54
Core Portability

• Determined by technology independence and data
  format.
• Technology independence based on the type of core
  
• both open and proprietary data formats are
  current in use.

DEF Design Exchange Format (Cadence) SPEF
Standard Parasitic Extended Format
(Cadence) GDSII Layout format (Cadence) ITL
Interpolated Table Lookup cell-level timing model
(Mentor) LEF Layout Exchange Format (Cadence)
MMF Motive Modeling Format (Viewlogic) NLDM
Non-linear Delay Model (Synopsys) TLF Table
Lookup Format (Cadence) VCD Verilog Change Dump
(Cadence) WGL Waveform Graphical Language (TSSI)
55
Current Core Market Models
Three ways

• 1. A design house licenses design and tools
• DSP Group (Pine and Oak Cores), 3Soft, ARM (RISC)
• offering includes HDL simulation model, tool
  and/or an emulator
• customer does the design, fab.
• 2. Core vendor designs and fabs ICs
• TI, Motorola, Lucent
• VLSI, SSI, Cirrus, Adaptec
• 3. Core vendor sells cores, takes customer
  designs and fabs ICs
• LSI logic, TI, Lucent

Licensable
Foundary Captive
Foundary captive cores do not have to reveal
internal design and layoutof the core. The
foundary provides a bounding box.
56
Core-based IC Systems

• Core supplier different from core user
• Third party IP providers
• Significant technology packaging without
  importing it
• The IP provider wants to sell a product and not
  the technology behind the product
• Enormous technical, and legal challenges
• can it be done successfully?
• who guarantees if a SOC works as required
• who is liable in case the end product does not
  perform?

57
ASIC Cores Availability

• LSI logic CoreWare
• IBM Microelectronics
• Motorola FlexWare
• Lucent

• 3Soft uC, DSP, LAN, SCSI, PI
• ARM uC, uP
• Plessey per. controllers, DSP
• Scenix uC, PCI, DMA
• Western Digital Center uC
• TI DSP NEC DSP, uC
• Symbios ARM7 TC
• VAutomation uP, controllers
• CAST 2910A, IDT49C410, DMAc

One-stop Shops

• Digital Design Dev MIDI
• Hitachi MPGE, PCI, SCSI, uC
• Palmchip MPEG, UART, ECC
• Silicon Engg. micro VGA

• Butterfly DSP DSP, FFT, DFT, ADSL, OFDM
• Int. Sil. Systems ADPCM, FIR
• Analog Devices DSP
• DSP Group Pine, Oak

• LogicVision BIST, JTAG
• ROHM UART, SIO, PIO, FIFOc, Add, Mpy, ALU
• Synopsys DesignWare, ISA, Intel uC
• Chip Express FIFO, RAM, ROM
• VLSI Libraries Memory, Mpy

• Eureka PCI Virtual Chips PCI, USB
• Logic Innovations PCI, ATM
• OKI PCI, PCMCIA, DMA, UART
• Sand USB, PCI
• Sierra ATM SAR, Ether, R3000

• Focus Semi PLL, VCXO
• VLSI Cores Encryption, DES
• ASIC Intl DES

NOT EXHAUSTIVE.
58
FPGA/CPLD Cores

• Generally capacity constrained cores
• do not include wide/high performance PCI, ATM
  SAR, or microprocessors
• Altera
• 8-bit 6502
• DMAC 8237
• PCI controllers
• APEX parts allow embedded system blocks with FPGA
• Xilinx
• PCI
• Actel
• System Programmable Gate Array (SPGA)
• combine FPGA with customer ASIC
• ASIC examples PCI router, DMA controller.

59
On-Chip Internet Applications

• Internet Tuner from iReady Corp.
• available as a licensable core design in Verilog
  HDL code
• Consists of
• network stack
• PPP, IP, TCP, UDP, ICMP
• email assist
• POP3, SMTP, MIME
• HTTP1.0, HTML3.2 support

Courtesy, iReady Corporation.
60
Digital Spread Spectrum RX using ARM

• Available from Sirius Corporation, Belgium
• Consists of
• ARM6 32-bit processor
• variable frequency IF downconverter
• chip matched filter
• seven parallel correlators
• UART connection, 14 programmable registers, 4
  kbit RAM
• Single-chip solution performs
• downconversion, demodulation, despreading, frame
  extraction and user interface
• Used in satellite receivers, wireless local loop
  receivers, positioning applications.

61
DIRAC Block Diagram
Courtesy Sirius Corporation.
62
Building Physical Layer Interface using PCI Cores

• Class of interface cores such as
• USB, UART, SCSI, PCI, 1394 etc.
• Identify target technology
• ASIC, FPGA,
• PCI
• processor independent CPU interface to
  peripherals
• multi-master, peer-to-peer protocol
• synchronous 8-33 MHz (132 MB/s)
• arbitration central, access oriented, hidden
• variable length bursting on reads and writes

63
PCI Cores

• VHDL/Verilog synthesizable cores with options
• PCI-Host, PCI-Satellite
• 32-bit (33 MHz) or 64-bit (66 MHz)
• FIFO or register data storage
• Synchronous or Asynchronous host interface
• Core components
• Master/Target Read/Write FIFOs,
• Master/Target State Machines
• Configuration registers
• Timing requirements
• input setup time 7ns clock to output delay
  11ns
• DC Specs input pin caps 10 pF, clk pin 12 pF,
  ID Sel 8pF

64
DSP Processors as Core Cells

• 16-bit fixed point processors are most commonly
  used.
• DSPs
• simple Clarkspur Design CD2450 (var data width)
• compatible DSPGroup, TI, SGS-T 320C5x
• clone
• Options
• memory, mem controller, interrupt controller,
  host port, serial port
• Criticals
• power consumption as most DSP applications go
  into portable products

65
Design using DSP Cores

• Core vendors often supply a development chip or
  core version of the COTS processor
• board-level prototyping fairly common
• followed by single-chip solution
• To avoid board-level prototyping, a
  full-functional simulation model is a must,
  particularly for foundary captive cores.
• Software tools provided
• assembler, linker, instruction set simulator,
  debugger, (high-level language compiler?)

66
DSP Sample Points

• TI TEC320C52
• 16-bit fixed-point TMS320C52
• 1Kx16 data RAM, 4Kx16 program RAM
• 2 serial ports, 1 16-bit timer
• and 0.8 micron 15,000-gate gate array
• Motorola 7-Day CSIC
• 8-16 MHz HC08, DMA, MMU, ..
• SGS-Thomson ST18932, ST18950
• 16-bit fixed-point DSPs, 0.5 u, 3.3 volt CMOS,
  80MHz
• has no off-the-shelf DSP IC
• used in PC sound cards, 950 has a better assembly

Not exhaustive, only a representative sample.
67
Third Party DSP Cores

• DSPGroup Pine
• 16-bit fixed-point, 0.8u CMOS, 5.0/3.3 V, 40 MHz
• 36-bit ALU, 16-bit MPY, 2Kx16 RAM/ROM, (prog mem
  is outside core)
• used in pagers and answering machines
• DSPGroup Oak
• same as Pine, plus includes a bit manipulation
  unit
• Viterbi decoding support instructions (min, max)
• used in digital cellular telephony
• Clarkspur CD2400, CD2450
• 16-bit fixed-point
• 24-bit ALU, MPY, Acc, 2x 256x16 data RAM/450
  makes it 48 bits
• used in fax-modem

68
One-Stop Shops LSI Logic CoreWare

• Cores for building ASIC for most embedded
  applications
• laser printer, ATM, PDA, Set-top, Router,
  Graphics accelerators, etc.
• CPU cores miniRISC CW4K, Oak DSP
• miniRISC compatible with MIPS R4000
• 0.5u CMOS, 2mW/MHz, 60MHz, 3-stage pipeline
• 32-bit address/data bus
• full scan 99 fault coverage, gate-level timing
  model
• Interface PCI, Fibre Channel, SerialLink
• Networking Ethernet, ATM (SAR), Viterbi, RS
• Compression etc MPEG, JPEG, DAC/ADC.

69
Core Examples

• Only a representative sample of cores. Not
  exhaustive or even comparative.
• Processor cores
• LSI Logic CW4001, CW4010
• ARM (7) processors
• Motorola FlexCore
• Memory cores
• 16M/18M Rambus DRAM
• Multimedia cores
• CompCore CD2
• Networking
• Media Access Controller (MAC)
• Encryption cores
• VLSI cores, ASIC international.

70
Advanced RISC Machines (ARM )

• A family of 32-bit RISC processor cores
• ARM6, ARM7
• MPU with Cache, MMU, Write Buffer and JTAG
• ARM7TDMI
• ARM7 with Thumb ISA, ICE, Debug MPY
• ARM8
• cached, low power, 5-stage pipe (vs 3 in others)
• StrongARM1, StrongARM2 available as Digital
  SA-110 (21285)
• Piccolo DSP co-processor for ARM, shares system
  bus (AMBA)
• support for Viterbi, bit manipulation operations
• four nestable zero-overhead hardware loop
  constructs
• splittable ALU, 1 cycle dual 16-bit operations
• saturation arithmetic
• 1024 point in place complex radix 2 FFT in 33,331
  cycles
• Manufacturing partnerships and/or licensing with
• Cirrus logic, GEC Plessey, Sharp, TI and VLSI
  Tech.

71
ARM Applications

• Widely used in a variety of portable applications
• low cost 16-bit applications
• mobile phones, modems, fax machines, pagers
• radio receivers
• hard disk and CD drive controllers
• engine management
• low cost 32-bit applications
• smart cards
• ATM and ethernet network interfaces
• low power, on-chip application code
• high performance 32-bit applications
• digital cameras
• set top boxes, network switches, laser printers
• external memory system (RAM, ROMs)
• Examples Olivetti wireless network computer,
  DIRAC SS RX

72
ARM Processor Cores

• Enhancements ARM7D, ARM7DM, ARM7DMI
• M 64-bit result hardware multiplier running at
  8bits/cycle
• D 2 boundary scan chains for basic debug
• I Embedded ICE debug
• Thumb instruction set

Source ARM Inc.
73
ARM Enhancements Embedded ICE

• The EmbeddedICE core cell allows debugging of ARM
  core embedded with an ASIC
• real time address and data-dependent breakpoints
• full access and control of the CPU
• can be reduced for size savings once the part
  goes into production.

74
ARM Enhancements Thumb ISA

• 8- or 16-bit external, 32-bit internal
• Thumb instruction set is a subset of 32-bit ARM
  instruction set
• 16-bit instructions
• expanded into 32-bit ARM instructions at run
  time without any penalty
• Upto 65-70 smaller code size compared to ARM
• 130 of ARM performance with 8/16 bit memory
• 85 of ARM performance with 32-bit memory

75
Motorola FlexCore

• CPU cores based on 680x0 family
• EC000, EC020, EC030
• all with static operation, 5/3.3 volt supplies
• performance
• EC000 2.7 MIPS _at_16.67MHz, 33 mW
• EC020 7.4 MIPS _at_25 MHz, 150 mW
• EC030 11.8 MIPS _at_33 MHz, 258 mW
• Serial I/O cores 68681UART, MBus, SPI
• RT clock, Dual timer cores
• SCSCI, Parallel I/O, 8051 interfaces
• DRAM, Interrupt, JTAG controllers
• PLA, PLL, oscillators, power management cells.

76
Memory Core Example

• Virtual Chips 16M/18M bit Rambus DRAM
• Verilog/VHDL simulation model
• Organization
• two banks, 512 pages per bank, 72x256 per page
• dual internal banks, 2K byte cache per bank
• Programmable ack, write, read delays through
  control registers
• Synchronous protocol for fast block oriented
  xfrs.
• Modes of operation
• reset, stand-by, power-down, active
• Deliverable VHDL, Verilog source, test bench,
  test vectors, documentations.
• Others Sand DRAM, VRAM verilog models.

77
Multimedia Cores

• JPEG compression, MPEG decoding, Video DAC, etc.
• IBM Microelectronics, LSI logic, PalmChip,
  Silicon Engineering, Mentor Graphics, CompCore,
  Intrinsix VGA
• Example MPEG-2 decoder from CompCore
• 70K-80K gates
• 18K bits of internal SRAM
• 16Mbit SDRAM (external)
• bitstream buffering, frames
• 54MHz, 16-bit external mem. bus

78
Other Core Categories
Networking
Encryption

• VLSI Cores
• PKuP encryption core
• implements modular exponentiation
• synthesizable HDL core
• DES core as a synthesizable Verilog model
• two models 8 bytes/8 cycle, 8 bytes/16 cycles
• ASIC International
• DES cores
• Exponentiator Engine
• Hash function cores

• Protocol choices
• switched Ether, s. TR, ATM155, ATM25
• Example SYM1000 from Symbios
• HDL code, 3.3 V, 0.5u
• CSMA/CD ethernet
• programmable inter-packet gap.
• Optional CRC insertion, and check
• MII interface to physical layer device
• Host bus interface
• LSI Logic ATMizer

79
Summary

• Design tools offerings for on-chip networked and
  wireless systems are an area of growing
  importance due to inherent complexity of on-chip
  design and multi-level tradeoffs
• Wireless system design tools are strongly
  influenced by the layer at which the design is
  being done
• System modeling tools are quite common and
  advanced
• Design environments, circuit design tools lag
  significantly behind the design practice
• At the physical level, the focus is on accurate
  on-chip modeling of parasitic effects.

80
References

• Models of computation
• http//ptolemy.eecs.berkeley.edu
• Language and methodology
• SpecC http//www.ics.uci.edu/specc
• OCAPI http//www.imec.be/ocapi
• Languages
• SystemC http//www.systemc.org
• CynApps http//www.cynapps.com
• CoWare http//www.coware.com
• Objective VHDL
• Language semantics
• R. Gupta and S. Liao, Using a programming
  language for digital system design, IEEE DT
  April-June 97
• Interface based design
• Alberto DAC97 Paper
• VSIA system level design workgroup
  http//www.vsi.org
• System level issue Gajskis silicon compilation
  and blue books
• Software design pattern book
• Architecture description language
  www.ics.uci.edu/aces/expression