Advanced VLSI Seminar 67696 Digital Design Flow

1
Advanced VLSI Seminar (67696)Digital Design Flow

• Itai Yarom
• March 9th 2006

2
Why should I attend at this seminar

• Easy grade.
• Tired of doing works and tests.
• Find a job.
• Learn what happen in the industry.
• All my friends are going.
• I heard good things on it.
• What is the goal of the seminar?
• To learn together the area of digital design flow.

3
Seminar principles

• Credit 2 points.
• Home page
• http//www.cs.huji.ac.il/jarom/vlsi_seminar/
• Time and location Thr. 10-12, Spr. 26.
• Duties
• To learn and present one subjects.
• Please send the slides by Wednesday midnight or
  bring them on disk-on-a-key to the class.
• To appear and participate in classes.
• To fill out feedback questionnaire.

4
What we had last year?

• 91 - ????? ????? ????? ???? ???? ???
• 97 - ????????? ??? ?? ??????? ???
• 96 - ????????? ??? ????? ???? ???????? ???
• 95 - ?????? ????? ??? ??????
• 100 - ????? ???? ?????? ????? ?????
• 100 - ????? ??? ???? ?????? ????????
• 100 - ???? ????? ?? ????? ??????

5
What is the biggest problem?

• To create bug-less design.
• To write efficient code.
• To build design that the customers will buy.
• To develop designs that are one generation ahead.

6
Moore law

• Moore law predicts that the number of transistors
  will double every 18 months.
• Last time Moore was asked whatever his law will
  stand for the coming decade, he said its
  accelerating.
• However, the designer efficiency is not growing
  that fast.

7
Closing the Design/Verification GAP

• We need technology leap in order to resolve this
  gap.
• HDL replaced the manually designing gate-level
  circuits.
• Which technology will resolve this gap?
• The goal of this seminar is to discuss
  technologies that can provide technology leap.

8
What is an HW design?

• Logic (ASIC) The logic of the design.
• IP Cores logic provided from previous project
  or other parties/companies.
• I/O Interface to the chip periphery.
• PLL Generates the clocks.
• Embedded CPU Core provide a way to run FW in
  the chip.
• Custom (analog) custom design elements.

9
The Basics of HW Design

• RTL (Register Transfer Logic) is the level used
  for HW design
• opposed to gate or behavioral design.
• Register is a state element (e.g., flip-flop).
• Transfer Logic is the logic that drives the
  register.
• Clocks activates the registers in the design.

10
How we develop HW?
Top level test
block level test

• Design a block.
• Verify the block design
• Block level testing (simulation).
• Integrate the blocks into top level design
• Top level verification
• Pre-silicon validation (simulation).
• Synthesize (to netlist)
• Layout
• Place and route
• Insert DFT elements
• Scan, BIST.
• Fabrication
• Silicon tests
• System level testing

Top-level design
block
Synthesis
netlist
Place Route
GDSII
Fabrication
silicon
Silicon tests
System level testing
11
Seminar Topics

• Electronic System Level (ESL)
• Virtual platform.
• Enhanced design language SystemVerilog
• Synchronizers/Clock Domain Crossing (CDC)
• Timing constraint verification (TCV)
• Electronic Change Order (ECO)
• Verification
• Assertion Based Verification (ABV)
• Coverage Driven Verification (CDV)
• Design For Test (DFT)
• Power
• Other

12
ESL

• Challenges are too hard for RTL level.
• Designs are complex.
• Tight relationships between HW and SW.
• Use (higher) transaction level modeling (TLM)
• Using SystemC language, based on C.

• Material
• A look inside electronic system level (ESL)
  design" "Mixed Abstraction Virtual System
  Prototypes Close SoC Design Gaps
• "High-level synthesis An Essential Ingredient
  for Designing Complex ASICs In-System FPGA
  Prototyping of an Itanium Microarchitecture"

13
Virtual Platform

• Complete System Level Modeling
• Ease of Use
• Performance
• Supports Standard SW Development Interfaces and
  Tools
• Material
• SoftSDV A Presilicon Software Development
  Environment for the IA-64 Architecture

14
System Level Modeling

• Verilog and VHDL are limited.
• Used as HDL (Hardware Description language) and
  additional verification language is needed.
• SystemVerilog will replace them both.
• SystemVerilog provides several advantages
• Concise less error, better readability.
• Statistics 2-3 bugs for 100 lines of code.
• Better reusability.
• Better verification.
• Better ownership support.
• Material
• SystemVerilog - Is This The Merging of Verilog
  VHDL?
• The Verilog PLI Is Dead (maybe) Long Live The
  SystemVerilog DPI!

15
Clock-Domain Crossing (CDC)

• Part of the Assertion based verification uses
  automatic checks.
• Typical modern chips have many clock domains,
  driven by
• SOC integration (more asynchronous clocks)
• Higher clock frequencies (skewed synchronous
  clocks)
• Clock-domain-crossing (CDC) effects can result in
  subtle, intermittent problems in silicon
• Verification hotspot with in-tool automation
• Cannot be verified using traditional techniques
• Requires Static Analysis, Simulation, and Formal
  Verification
• Material
• Verifying Synchronization in Multi-Clock Domain
  SoC

16
Timing Constraint Verification

• The implementation flow of synchronous design
  uses timing assumptions
• Clock frequencies
• There are paths that dont meet the assumptions
• False-paths.
• Multi-Cycle paths.
• How can we verify those paths?
• Material
• Automatic Verification of Timing Constraints

17
Assertion Based Verification (ABV)

• Improve the simulation process.
• Improve observability.
• Improve controllability.
• The designer implement assertions in the design.
• The assertions are checked with
• Simulation.
• Formal techniques.

• Material
• Leveraging Assertion Based Verification by using
  Magellan
• A Unique Functional Coverage Flow using
  SystemVerilog and NTB
• Functional formal verification on designs of
  pSeries microprocessors and communication
  subsystems

18
Coverage Driven Verification (CDV)

• The biggest gap is the verification gap.
• How can a verification team verify large and
  complex designs?
• Write tests that will check the functionality of
  the unit.
• Many tests hard work.
• Write an engine that will generate valid tests.
• Better ROI (Return on Investment).
• How can the verification team be sure that their
  tests are efficient?
• Material
• Indicators help manage coverage-driven
  verification

19
Challenges of submicron verification

• The world is silicon testing.
• Small geometrics creates new challenges and
  silicon defects.
• New test technique are needed
• Speed related test (_at_speed tests)
• Test compaction techniques
• Material
• TBD

20
Seminar Topics

• Electronic System Level (ESL)
• Virtual platform.
• Enhanced design language SystemVerilog
• Synchronizers/Clock Domain Crossing (CDC)
• Timing constraint verification (TCV)
• Electronic Change Order (ECO)
• Verification
• Assertion Based Verification (ABV)
• Coverage Driven Verification (CDV)
• Design For Test (DFT)
• Power
• Other

21
Seminar Topics (2005)

• Assertion based verification (ABV)
• Clock domain Crossing (CDC)
• System Level modeling
• Challenges in ECO (Electronic Change Order)
• Random Verification of large designs
• Challenges of submicron verification
• Test flow for at-speed testing
• Solving the verification gap
• Test compaction techniques.
• RTL to GDS flow.