The SLHC CMS L1 Pixel Trigger

1
The SLHC CMS L1 Pixel Trigger Detector Layout

• Wu, Jinyuan
• Fermilab
• April 2006

2
Preference on Detector Layout

• Pixel planes are expensive in terms of material,
  cost, data volume, power, cooling etc. (C3 Cost,
  Cable, Cooling)
• If N layers of pixel detector planes are
  affordable, normally spaced configurations like
  (b) is more preferable for data analysis stage.
• Pattern recognition for (b) is more difficult ?.
• From BTeV works, the pattern recognition for (b)
  is not as hard as we thought several years ago ?.

(a)
(b)
3
Brief History of Tracking

• Long time ago, tracking was done by
• Finding 2-point candidates (doublets) and then
• Finding the third point.
• Before BTeV, it was known
• Triplet can be found in one step.
• During BTeV, we learnt how to do triplet finding
  in FPGA fast and cheaply. (e. g. Tiny Triplet
  Finder)

4
Circular Tracks from Collision Pointon
Cylindrical Detectors
(F2-F3)64
(F1-F3)64

• For a given hit on layer 3, the coincident
  between a layer 2 and a layer 1 hit satisfying
  coincident map signifies a valid circular track.
• A track segment has 2 free parameters, i.e., a
  triplet.
• The coincident map is invariant of rotation.

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Tiny Triplet FinderReuse Coincident Logic via
Shifting Hit Patterns
C3
C2
C1
One set of coincident logic is implemented.
For an arbitrary hit on C3, rotate, i.e., shift
the hit patterns for C1 and C2 to search for
coincidence.
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Tiny Triplet Finder for Circular Tracks
Also works with more than 3 layers
Shifter
Shifter
Bit-wise Coincident Logic
Bit Array
Bit Array

• Fill the C1 and C2 bit arrays. (n1 clock cycles)
• Loop over C3 hits, shift bit arrays and check for
  coincidence. (n3 clock cycles)

R1/R3
R2/R3
Triplet Map Output To Decoder
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Question How can data fromdifferent layers
merge together?

• Total data rates from pixel layer _at_ 10cm are
  3.125, 5 or 12 Gb/s/cm2.
• To send full data over large distance is
  difficult. (The good side of stacked layer ideas
  is the possibility of doing coincident locally.)
• Difficult, yes, but there are several
  possibilities.

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Possibility 1

• Pre-trigger

9
From LHC to SLHC

• The total L1 latency for SLHC has been increased
  to 6.4 us.
• Total L1 rate is kept the same (100kHz).
• Consider a pre-trigger of 1MHz _at_ 3.2 us.
• Use pre-trigger to dump data from pixel.
• Data rate 1/80 or 1/40.

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Sending Data to Triplet FinderThe Pre-trigger
ECAL
L1
ROC
Triplet Finder
ROC
HLT DAQ
ROC
ROC
3.2us
ECAL Pre-trigger
ECAL finer trigger
Cable
L1 trigger
Cable
Cable
L1 PT
Cable
ROC out
Cable
L1 trigger
Cable
Triplet Trigger

• ECAL (or any other) generates coarse pre-trigger
  and sends to global L1.
• The pre-trigger is distributed to all (or 1/2,
  1/4 of all) readout chips at 3.2 us. The
  distribution lines are original L1 trigger signal
  lines.
• The ROC output data and the tracker trigger
  generates trigger primitives.
• The L1 system makes final global T1.
• Pre-triggered data stored in Tracker Trigger
  during the second 3.2 us are sent to HLT/DAQ.
  ROC has shorter pipeline in this operation mode.
• Worst case two round trips. Better if one round
  trip can be eliminated.

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Some Numbers
ECAL
L1

• Assume ECAL generates up to 1MHz pre-trigger
  with 3.2us latency.
• Use the hit rate 4hits/(1.28cm)2/BX _at_ R8cm.
• Total data rate 4hits x 16 bits/hit x 1MHz 64
  Mb/s.
• Assume each (1.28cm2) ROC output Cu pairs _at_ 160
  Mb/s.

ROC
Triplet Finder
ROC
HLT DAQ
ROC
ROC
3.2us
ECAL Pre-trigger
ECAL finer trigger
Cable
L1 trigger
Cable
Cable
L1 PT
Cable
ROC out
Cable
L1 trigger
Cable
Triplet Trigger
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Possibility 1

• Pre-trigger
• Stacked layers for high PT tracks

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High PT Doublet Finding, If Needed
ECAL
R300mm
L1
R295mm
ROC 300
Triplet Finder Readout
ROC 295
HLT DAQ
R200mm
ROC 200
ROC 100
Readout Only
ROC 50
R100mm

• The system supports both ECAL pre-trigger mode
  and high PT doublet finding mode.
• The ROC at 300mm and 295mm communicate to each
  other.
• High PT doublets are found in ROC.
• The doublets point the searching windows on 200
  and 100mm layers and hits in the window are
  enabled to be readout.
• One set of stack layers, rather than 3.

R50mm
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Stack Layers 1mm or 5mm

• Pixel pitch Du in f, Dv in z.
• Layer separation (r2-r1).
• Measurement error
• Df Du / (r2-r1)
• Dh Dv / (r2-r1)
• Power Consumption
• P P0 A /(Du Du).
• Therefore
• P Df Dh P0 A / (r2-r1)2.
• When the layer separation increases from 1mm to
  5mm, P Df Dh reduces by factor of 25.

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Straw Man Stack Layers (r-z view)
Sensor
Readout Chip
Mechanical Support, Cooling, interconnection
Readout Chip
Sensor
Coincident Range
Seeding Hits

• The two stack layers share same mechanical
  support and cooling layer.
• ROC in two layers overlap to each other in z
  direction. Hits from 1/4 of chip at both end are
  sent to opposite chips for coincident.
• Questions overlapping in phi direction?

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Straw-Man Readout Chip -- Backend
Column Logic Zero Suppression
Pipeline
6.4us
3.2us
1.0us
DOUT
High PT Segment Correlation
CS64 CS32
CS10
HDA
CS10A
HDB
T1orPT
From/to Stack Layer ROC
From L1
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Pipeline and CS32/64
Column Logic Zero Suppression
Pipeline
6.4us
3.2us
1.0us
DOUT
CS64 CS32
T1orPT
From L1

• The hit data are stored in the pipeline.
• After 3.2 us, when the pre-trigger comes (signal
  T1orPT), the ROC sends data out for triplet
  trigger.
• After 6.4 us, when the L1 comes, the ROC sends
  data of the BX out.

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High PT Correlation
Plane A
Bit Enable Register
Plane B

• The OR-AND coincident logic accepts high PT
  doubles.
• Set the Bit Enable Register to change PT cut and
  correct offset on pixel alignment.
• The OR gate is replaced with a priority encoder
  in real implementation.

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1 Copy, Not 256 Copies in real implementation
Plane A
Logarithmic Shifter
Priority Encoder
Plane B

• Some design may use N copies of coincident logic.
  (N256 here.)
• The design here uses 1 copy.
• Note that Plane A is local in the ROC and Plane B
  is another ROC. The data from Plane B are column
  coordinate of hits.
• The priority encoder output represents track
  angle.

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About This Work

• It is extremely interesting since it is still in
  detector layout stage. There are not so many
  chances one can work at this stage in ones life
  time.
• Simulation, simulation, simulation.
• Time is tight. (TDR around 07, 08)

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The EndThanks
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Analysis
(a)
(b)

• Track reconstruction
• Impact parameter.
• Transverse momentum.
• Fake track rejection
• Compare configuration (a) and (c) when silicon
  strip tracker data are also included.

(c)