Complete Design of a USB 2'0 Peripheral

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Complete Design of a USB 2.0 Peripheral using
Spartan-3 FPGA
Esfahan University of Technology Department of
Electrical Computer Engineering September
2007
Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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Why USB?

• Easy to Use
• Speed
• Reliable
• Expandable
• Power-conserving
• Supported by the Windows and other OS

Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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Endpoints

• sources or sinks of data

Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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Transfer/Endpoint Types

• Control
• command and status operations
• Interrupt
• non-periodic, device-initiated communications
  requiring bounded latency
• Isochronous
• contain time sensitive information
• guaranteed access to USB bandwidth
• Bulk
• large bursty data
• error detection/re-transmission

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Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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Enumeration

• The process of determining what device has just
  been connected to the bus and what parameters it
  requires. This is done by sending the descriptor
  to host.
• Descriptor
• All USB devices have a hierarchy of descriptors
  which describe to the host information such as
• what the device is
• who makes it
• what version of USB it supports
• how many ways it can be configured
• the number of endpoints and their types

Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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USB Descriptors
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Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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USB Controllers

• - low level USB signaling a protocol handling
  and management system
• - An interface which connects the previous
  sections to the rest of the system
• Stand alone controllers
• USB controllers which rely on an external master.

Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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CY7C68001 EZ-USB SX2

• a slave device controlled by an external master
• built-in USB transceiver and Serial Interface
  Engine
• command decoder for sending and receiving USB
  data
• automatically responds to USB standard requests
  without any external master intervention

Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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CY7C68001 EZ-USB SX2

• SX2 Interfaces
• - FIFO interface - Synchronous
• - Command interface - Asynchronous
• Endpoints
• 1- Control endpoint
• - 64 Bytes - endpoint 0
• 2- FIFO endpoints
• - 4096 bytes (8512 bytes) , which is shared
  between up to 4 endpoints (endpoints 2, 4, 6 and
  8).

Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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FPGA SX2 Connection
Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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FPGA Side
SX2 is mainly designed to be connected to
microcontroller like devices.

• Different Choices
• - PowerPC hard core
• - MicroBlaze soft core
• - PicoBlaze soft core

Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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PicoBlaze

• very simple 8-bit microcontroller
• occupies just 96 spartan-3 slices which is just
  5 of XC3S200 device and less than 0.3 of
  XC3S5000 device.

Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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Two Choices

• 1) PicoBlaze
• - FPGA resource utilization of less than 100
  slices
• - limited transfer rate of up to 100MBits/s
• - SX2 is configured to use its own internal
  clock source
• - data transfers between FPGA and SX2 will be in
  asynchronous mode.
• 2) PicoBlaze High Speed Logic
• - resource usage of above 350 slices
• - higher performance of more than 400MBits/s
• - synchronous data transfers between FPGA and
  SX2 will be done using an FPGA provided clock
  source.

Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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System Block Diagram (1)
PicoBlaze
IOInterface
DataManager
Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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PicoBlaze Execution Flow in the first design
Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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System block diagram (2)
Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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Clock generator block diagram
Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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PicoBlaze Execution Flow in the second design
Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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FSM
Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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FSM Transitions
Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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I/O Interface
controlling the I/O pins connected to SX2

• Four sources of data
• DESC, PICOBLAZE, WRITEFIFO FSM
• Two sources of control signals
• PICOBLAZE FSM
• Data received from SX2 is sent to FSM and
  READFIFO through this module

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Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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PC Side Software

• CyUSB for Windows
• Libusb for Windows
• Libusb for Linux

Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh
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Highest possible data rates
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Mohammad Sadegh Sadri,Fatemeh ArbabJolfaee,Fatemeh
FaniSani,Neda Mohammadizadeh