EECE 631 Microcomputer System Design Lecture 16

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EECE 631Microcomputer System DesignLecture 16

• Spring 2007
• Chris Lewis
• clewis_at_ksu.edu

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ISR Initialization

• AT91F_AIC_Open()
• AT91F_AIC_ConfigureIt()
• AT91F_AIC_ClearIt()
• AT91F_AIC_EnableIt()
• for(int i0 ilt8 i) pAIC-gtAIC_EOICR 1
  //acknowledge an interrupt to clear it
• __set_CPSR(0x5F) //clear bit I in the CPSR
  to start interrupts working

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Paper Design

• The Paper Design includes some or all of the
  following
• Description of Device
• Executive Summary
• Users Manual
• Schematics
• High Level Algorithm
• Parts requirements
• Processor selection
• Description of extent of expected completion of
  each aspect of project
• Schematics done with Board layout package
• Board layout
• Board printed, populated and working
• Breadboard, use lab cpu
• Test plans
• Milestones

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Oral Progress Report

• Somewhat formal
• Give the report as if you are working under
  contract with a customer. The customer has come
  to see how things are going. Your job is to let
  them know.
• Review original scope of project
• State progress relative to original milestones
• Illuminate special unforeseen challenges, but
  dont dwell on them
• Honest assessment of ability to meet final goals

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Final Demonstration

• Somewhat formal Significant part of overall
  project grade
• Present your work in its best light
• Emphasis your accomplishments
• Start by describing the idea behind your project.
  
• First prototype
• Proof of concept
• Working Model
• Illuminate the performance of your system with
  results from your test-plan
• Illuminate the performance of your system with a
  live demonstration of the important features

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Final Report

• Significant part of overall grade
• Hard and soft copy
• Overview of device
• Pictures of device and possibly scope
• Schematics and board drawings
• Flowcharts
• Summarize level of completion
• Users manuals if appropriate
• Notes to future developers
• Anything you spent significant time discovering
• Outline method for initializing device
• Code listing in electronic format
• Level of effort for division of Labor
• Usually this is 50/50, or extraordinary effort it
  recognized by both
• If you oppose your partners view, submit
  paragraph directly to me.

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My Role in your project

• Debugging
• Technical advice
• Find resources
• You are ultimately responsible for the final
  outcome of your project
• You are responsible for getting along with and
  determining responsibilities of your partner
• You are responsible for source code control
• Partners receive same grade unless
• Obvious to me that one blatantly under performed
• Report indicates a substantial difference in
  effort
• Assigning grades

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IDE Custom Config

• ioat91sam7s256.ddf
• Sfr
• Register definition for SYS
  peripheral
• Register definition for AIC
  peripheral
• sfr "AIC_SMR0", "Memory", 0xfffff000, 4,
  base16
• sfr "AIC_SMR0.PRIOR", "Memory", 0xfffff000, 4,
  base16, bitRange0-2
• sfr "AIC_SMR0.SRCTYPE", "Memory", 0xfffff000,
  4, base16, bitRange5-6
• sfr "AIC_SMR1", "Memory", 0xfffff004, 4,
  base16
• sfr "AIC_SMR1.PRIOR", "Memory", 0xfffff004, 4,
  base16, bitRange0-2
• sfr "AIC_SMR1.SRCTYPE", "Memory", 0xfffff004,
  4, base16, bitRange5-6
• sfr "AIC_SVR0", "Memory", 0xfffff080, 4,
  base16
• sfr "AIC_SVR1", "Memory", 0xfffff084, 4,
  base16
• sfr "AIC_IVR", "Memory", 0xfffff100, 4,
  base16
• sfr "AIC_FVR", "Memory", 0xfffff104, 4,
  base16
• sfr "AIC_ISR", "Memory", 0xfffff108, 4,
  base16
• sfr "AIC_IPR", "Memory", 0xfffff10c, 4,
  base16
• sfr "AIC_IMR", "Memory", 0xfffff110, 4,
  base16

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Remaining Topics

• Timing
• Adding external memory or peripherals
• General Discussion of RTOS topics
• Report writing
• Overview of History and State of
  micro-controllers, role of FPGAs etc.
• Suggestions?
• USB
• DSP Overview

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Timing

• Want to add a memory element
• Memory
• Peripheral
• Can the CPU work with that device?
• Insure that it will always work, not just
  typically work
• How many wait states are required?

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Basic Idea of Timing

• A signal originates from one chip
• A signal is required by another chip
• Originating chip gives time specifications that
  it guarantees it will meet.
• These guarantees are ultimately related to a
  clock signal, but often given relative to another
  signal
• Receiving chip gives timing requirements on
  signals.
• These requirements are ultimately related to a
  clock signal, but often given relative to another
  signal.
• Often chips perform much better than the
  specifications provided. That is, a memory chip
  will work even though it is not guaranteed to do
  so.. Until it gets too hot/cold etc.
• Always design to max/mins, not to typicals.

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Simple Example

• Consider a clocked flip flop
• Set up time How long stable input prior to clock
• Hold time How long stable input after clock
• What happens if these conditions not met?

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Rise and Fall times 10-90
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AT91SAM7SE (external memory)
Clock Clock Enable Chip Select Bank Select Row
Signal Column Signal Write enable Data mask
enable Address Data
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SDRAM controllerSDRAMC
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What is this?
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Table of Specs
Clock enable guaranteed to be stable (high)
before a Rising edge of the clock Clock enable
guaranteed to remain stable (high) after rising
edge of clock Same for low