USB 2.0 Transceiver Macrocell

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USB 2.0 Transceiver Macrocell

• Steve McGowan - Intel Corporation
• Clarence Lewis - Texas Instruments

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Macrocell Requirements
Overview

• Simplify the design process for peripheral
  vendors
• Consolidate high speed logic in to a discrete
  module
• Provide a standard USB 2.0 hardware interface
• Minimize time to market
• Decouple ASIC and Peripheral development cycles
• Enable standard library elements from ASIC
  vendors
• Peripheral vendors can focus on productspecific
  development
• Reuse of existing USB 1.1 SIE logic

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USB Device Development
Overview

• Assumptions
• Prototyping
• FPGA
• UTMI Compliant Discrete Transceiver
• Production
• Low Volume
• Gate Array
• UTMI Compliant Discrete Transceiver
• High Volume
• ASIC
• UTMI Compliant Transceiver Macrocell

High Volume Means Single Chip Solutions
Open Specification
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Device Anatomy
Overview

• USB Transceiver Macrocell (UTM)
• Serial Interface Engine
• Device Specific Logic

UTM Interface
ASIC
Serial Interface Engine
DeviceSpecificLogic
Device Hardware
Endpoint Logic
SIE Control Logic
USB 2.0
USB 2.0 Transceiver
Endpoint Logic

Endpoint Logic
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Serial Interface Engine
Overview

• SIE Control Logic
• USB Transaction State Machine
• PID, Address, and EP match logic
• Checks receive completion status
• Chains packets into transactions
• Endpoint Logic
• FIFOs and FIFO control

Minor Protocol Changes from 1.1
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Transceiver Macrocell
Overview

• Converts USB signaling into a simple interface
• USB 2.0 compliant serial interface
• Multiple Parallel Data Interface Options
• Multiple Speed Options
• HS/FS, FS Only, LS Only

Macrocell Handles Signaling
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Macrocell Functions
Overview

• HS and FS signaling and termination
• HS receiver squelch
• USB clock recovery
• Bit stuffing
• NRZI encoding
• Serializing and deserializing
• Data-rate tolerance
• Data buffering
• Single interface for HS/FS, FS or LS operation

Consolidates High Speed Clock Domain
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Block Diagram
Shared Logic Used by FS and HS
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8-Bit Uni-Directional
Interface Options
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16-Bit Uni-Directional
Interface Options
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16-Bit Bi-Directional
Interface Options
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Macrocell Functions

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Interface
Macrocell Functions

• Packet Engine
• Automatically handles SYNC Pattern and EOP
• Flow Control
• Compensates for Bit Stuffing and Data Rate
  Tolerance
• Primitives for Full Protocol Support
• Speed Switching
• Clock Generation
• Power Control

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Receive
Macrocell Functions

• RXActive - Frames Packet
• RXValid - Provides Flow Control

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Transmit
Macrocell Functions

• TXValid - Frames Packet
• TXReady - Provides Flow Control

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Signals
Macrocell Functions

• Flow Control
• Receive with data underruns due to removing
  stuffed bits from the data stream

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Protocol Primitive Support
Macrocell Functions

• Resume Assertion
• Resume Detection
• Suspend Detection
• Reset Detection
• HS Detection Handshake

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Operational Modes
Macrocell Functions

• Normal Operation
• Standard encoding and decoding of serial stream
• Non-Driving
• Tri-states all transmitters and termination on
  the bus
• Unencoded Data (needed for test modes)
• Disable Bit Stuffing and NRZI encoding
• Allows transmission and reception of unencoded
  data

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Resume Assertion
Macrocell Functions

• Place Macrocell in Disable Bit Stuffing and NRZI
  encoding mode
• Transmit 0 data for Ks (1 data for Js)
• Wait for SE0

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Resume Detection
Macrocell Functions

• Listen to LineState
• Use J to K transition to disable SuspendM
• Enter HS mode after K to SE0 transition
• Assert XcvrSelect and TermSelect

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Suspend Detection
Macrocell Functions

• Watch LineState for 3ms of inactivity (SE0)
• Switch to FS mode
• Assert XcvrSelect and TermSelect
• If J asserted, then enter Suspend State
• Assert SuspendM

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Reset Detection
Macrocell Functions

• SE0 is the Idle state in HS mode
• After 3ms of inactivity (SE0) switch to FS mode
• Assert XcvrSelect and TermSelect
• If SE0 asserted then enter Reset
• Initiate HS Handshake Detection

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HS Detection Handshake
Macrocell Functions

• Turn on HS Transceivers with FS Terminations
• Drive a Chirp K
• Detect Chirp K/J Sequence from the Hub
• Assert HS Terminations

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Clock Generation
Macrocell Functions

• Macrocell supplies clocks to the SIE
• Frequency depends on implementation
• HS/FS
• 60 MHz 8-bit uni-directional
• 30 MHz 16-bit uni- or bi-directional
• FS Only
• 48 MHz 8-bit uni-directional
• LS Only
• 6 MHz 8-bit uni-directional

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Power Control
Macrocell Functions

• SuspendM signal
• Shuts down clocks
• Maintains terminations
• Vendor determined Drive Current Control
• Enabled during transmits
• Enabled by receives
• Always on

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Next Steps

• Get the USB 2.0 Transceiver Macrocell Interface
  (UTMI) Specification
• http//developer.intel.com/technology/usb/
• 1.0 Release Available
• No Royalty
• Develop to the UTMI Specification
• Get your ASIC vendors to provide a UTMI Compliant
  Macrocells
• steve.mcgowan_at_intel.com

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