Low Power Modes, Interrupts and Resets

1
Low Power Modes, Interruptsand Resets

• ME6405
• Paul Lowe
• Al Khalique Hamilton
• Lucas Loriot
• Michael Murphy

2
Overview

• General information
• Polling Interrupts

• Paul
• Al Khalique
• Lucas
• Mike

Non-Maskable Interrupts Resets
General Process Maskable Interrupts Low Power
Modes
Demonstration
3
Polling vs. Interrupts
BRRRINNGGG!!!!!!!

• CASE A
• Periodically pick up phone
• CASE B
• Wait for the phone to ring

4
Polling
memory address
Data Bus
CPU
Polling
I/O Device
I/O Device
5
Polling - Example

• LOOP LDAA PORTA
• BEQ LOOP
• LSR A
• BCS ADDR0
• LSR A
• BCS ADDR1
• BRA LOOP

6
Polling Example cont

• LOOP LDAA PORTA
• BEQ LOOP
• LSR A
• BCS ADDR0
• LSR A
• BCS ADDR1
• BRA LOOP

7
Polling

• Pluses
• Simple Handshaking Technique
• No additional hardware needed
• Efficient for simple scenarios (i.e. one I/O
  operation.

• Minuses
• Inefficient in a real-world environment
• May not be fast enough to satisfy service reqs
• Difficult to maintain when multi-tasking

8
Interrupts
9
Interrupts
CPU
Controller
device driver initiates I/O
controller initiates I/O
CPU receives interrupt
Input ready, output complete or error generates
interrupt
ISR process data and RTI
Flexibility Generality
CPU resumes interrupted task
10
Which Device requested the Interrupt?

• Polling Interrupts
• Software Driven
• Chaining
• Level Sensitive
• Vectored (Hardware Identification)
• PICs
• Fastest

11
When do we use Interrupts?

• I/O data transfers for peripheral devices
• Input signals to be used for timing purposes
• Emergency situations (power-downs)
• Multitasking
• Event-driven programs
• Power failure
• RC circuit senses impending power loss and
  switches to batter backup

12
Real World Examples

• Pressing a pause button on a VCR (IC)
• Compiler recognizes an error (illegal opcode
  trap)
• Input capture of optical encoder for a DC motor
  (lab 5)
• Set a light to go on in a certain time (timers
  lecture)

13
Interrupt Features

• Interrupts can be ignored (or masked)
• multitasking
• when mask is set, interrupts are hidden
• Interrupts can be prioritized
• fire alarm, then oven timer, phone rings, etc
• Non- Maskable Interrupts can not be ignored.

14
Interrupt Disadvantages

• Interrupts can occur randomly (unanticipated)
  therefore debugging can be difficult.
• Tradeoff between hardware since driven hardware
  device can be complex.

15
Interrupts Flow Chart
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Interrupts Stacking Order
SP After Operation
SP-9
SP-8
CCR
SP-7
ACCB
SP-6
ACCA
SP-5
IXH
SP-4
IXL
SP-3
IYH
SP-2
IYL
SP-1
PCH
SP Before Operation
SP-0
PCL
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Interrupts Vectors
 
 
 
 
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Interrupts Vectors and RTI

• Example
• SWI vector
• use of RTI

ORG C000 LDX C100 STX FFF6 END ORG
C100 RTI
Main Program
. . .
SWI Service Routine
. . .
19
Interrupts RTI

• RTI - ReTurn from Interrupt
• is present at the end of every interrupt service
  routine
• terminates the interrupt
• pulls register values off of the stack
• program continues where it left off before
  interrupt

20
Interrupts Types

• 6 Non-Maskable
• always interrupt the program execution
• 15 Maskable
• can enable or disable by mask bits

21
Non-Maskable Interrupts

• Priority

• Reset
• Clock Monitor
• COP Watchdog
• Illegal Opcode
• XIRQ
• SWI

NOTE With the exception of XIRQ, these
interrupts do not possess a mask in the CCR,
hence their name However, some are enabled by
software
22
Resets

• Used to force MCU to reset and assume a set of
  initial conditions
• Allows for an orderly software start-up from a
  predetermined starting address
• Initialize the state of the system by
  initializing SP and control registers
• Similar to interrupts, except they dont save any
  states

23
System Initial Conditions

• CPU
• Fetches restart vector from FFFE, FFFF
• Stack pointer and other registers are
  indeterminate immediately after reset
• X and I bits in CCR are set to mask any interrupt
  requests
• S bit in CCR set to disable the STOP mode

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System Initial Conditions

• Memory Map
• INIT register initialized to 01
• 256 bytes RAM located at 0000-00FF
• Control registers located at 1000-103F
• Parallel I/O
• All ports reset
• Port C initialized as an input port

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System Initial Conditions

• Timer
• Count initialized to 0000
• Prescalar bits cleared
• All output-compare registers set to FFFF for
  initialization
• All input-capture registers are indeterminate
• Mode of Operation
• Established during reset (single chip, expanded,
  etc.)

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System Initial Conditions

• Several effects of reset
• Real-Time Interrupt
• Memory Map
• Pulse Accumulator
• COP Watchdog
• Serial Communications Interface (SCI)
• Serial Peripheral Interface (SPI)
• A/D converter

27
Sources of Resets

• External RESET pin
• Power-on reset
• Computer operating properly (COP) watchdog timer
  reset
• Clock monitor reset

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RESET pin

• When reset condition sensed, pin is driven low
  for 4 E clock cycles then released
• Pin is sampled 2 E clock cycles later
• If still low system assumes external reset has
  occurred
• else reset was initiated internally by either
  the COP watchdog timer or the clock monitor

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RESET pin usage

• Should be held low (by an external circuit) while
  VDD is below minimum operating level to protect
  EEPROM from corruption
• This minimum level should exceed 4.6V to prevent
  accidental overwriting of EEPROM

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Power-on Reset (POR)

• Initializes internal MCU circuits when positive
  transition is detected on VDD
• Triggers internal timing circuit that holds RESET
  pin low for 4064 cycles of the internal clock
• This delay after the oscillator becomes active
  allows the clock generator to stabilize

31
COP Watchdog Timer Reset

• Reset occurs when watchdog times out (not reset
  in specified time period)
• Intended to detect software processing errors
• Enabled by clearing NOCOP bit of CONFIG register
• Software must periodically clear watchdog timer

32
Servicing the COP Timer
Address 103A, COPRST Register

• Two steps
• Write 55 to COPRST register
• to arm the clearing mechanism
• Write AA to the COPRST register
• Any number of instructions can be performed
  between the two steps
• Must be performed in the correct sequence before
  the timer times out
• COP timer can be scaled to allow longer time
  period for timeout (in normal mode, this scaling
  must be done in first 64 clock cycles after reset)

0
1
0
1
0
1
0
1
0
1
0
1
0
1
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COP Watchdog Rates

• Set by bits CR1 and CR0 in COPRST register

34
Clock Monitor Reset (CMR)

• Detects a slow or stopped E clock
• An E-clock frequency below 10 kHz is detected as
  a clock monitor error
• E-clock frequencies of 200 kHz or more prevents
  clock monitor errors
• Enabled by setting the CME bit in OPTION
• Useful as a backup for the COP watchdog because
  CMR requires no clock while COP does

35
Nonmaskable Interrupts

• Illegal Opcode
• Nonmaskable Interrupt Request ( XIRQ )
• Software Interrupt (SWI)

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Illegal Opcode

• When illegal opcode is detected, interrupt is
  requested to the illegal opcode vector
• When interrupt service is complete, SP should be
  reinitialized to prevent repeated execution of
  illegal opcodes
• If uninitialized, the illegal opcode vector can
  point to a memory location that contains an
  illegal opcode, causing an infinite loop that can
  ultimately crash system

37
XIRQ

• Useful b/c they can always interrupt CPU
  operations
• Commonly used for serious system problems, ie.,
  power failure or program runaway
• Enabled with software by clearing X bit in the
  CCR with a TAP instruction
• After being cleared, X bit cannot be set by
  software, so XIRQ is non-maskable
• Higher priority than any source that is maskable
  with the I bit

38
XIRQ

• When an X bit interrupt occurs, both the X bit
  and the I bit are set by hardware
• RTI instruction restores the X and I bitsSoftware
  Interrupt (SWI)
• Executed in same manner as any other software
  instruction
• Only takes precedence over interrupts if they are
  masked
• Similar to interrupts
• Sets the I bit
• CPU registers are stacked
• Uses vectoring

39
Maskable Interrupts

• Most interrupts are maskable
• Masking an interrupt prevents its execution
• If the I bit of the CCR is 1, all maskable
  interrupts will be disabled
• Many maskable interrupts require flags to be set

40
Maskable Interrupts Priority

• Order of priority
• IRQ
• Real-time interrupt
• Timer input capture 1
• Timer input capture 2
• Timer capture 3
• Timer output compare 1
• Timer output compare 2
• Timer output compare 3
• Timer output compare 4
• Timer IC4/OC5
• Timer overflow
• Pulse accumulator overflow
• Pulse accumulator input edge
• SPI transfer complete
• SCI system

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Maskable Interrupts HPRIO

• Can elevate the priority of one of the maskable
  interrupts
• Uses bits 0-3 of HPRIO (Highest PRIOrity
  interrupt register)
• Default is IRQ
• Can be set at anytime during program as long as I
  bit is set

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Maskable Interrupts HPRIO
HPRIO 103C
 
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Maskable Interrupts The I Bit

• Bit 4 in the Condition Code Register (CCR)
• When Set
• interrupts can become pending but will not be
  honored
• When Cleared
• interrupts enabled to interrupt normal program
  flow when requested to

44
Maskable Interrupts The I Bit

• Set during RESET to allow minimum system
  initialization
• Set upon entry into any interrupt service routine
• Can also be set by software to prevent execution
  of maskable interrupts
• SEI (SEt Interrupt mask)

45
Maskable Interrupts The I Bit

• Can be cleared by software instructions
• CLI (CLear Interrupt mask)
• nesting of interrupts possible by clearing I-bit
  during an interrupt service routine (not
  recommended)
• Is automatically cleared by RTI instruction

46
Maskable Interrupts IRQ

• Controlled by a pin on the HC11
• A low signal will initiate interrupt sequence

Option 1039
Bit 7 6 5
4 3
2 1 Bit 0
ADPU
CSEL
IRQE
DLY
CME
CR1
CR0
IRQE IRQ Select Edge Sensitive Only (Time
Protected) 0 IRQ configured for low LEVEL
(default) 1 IRQ configured for falling
EDGEs
47
Maskable Interrupts Peripheral Subsystems

• Some require a specific bit in a register to be
  set in order to generate interrupt
• When flag goes high, interrupt is triggered
• Different methods to reset flag - depends on flag

48
Low Power Modes (LPM)

• Are used to reduce the power consumption of the
  controller.
• Two modes
• WAIT
• STOP

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LPM Wait Mode(I)

• Instruction Code (WAI)
• Machine State is Stacked
• Program is stopped
• Oscillator continues to run
• Exit wait state through RESET or Non-maskable
  interrupt

50
LPM Wait Mode

• Additional Power Reduction Options
• I bit set and COP disabled then free-running
  timer system is turned off
• Clearing ADPU in OPTION register turns off A/D
  converter
• SPI and SCI systems can also be disabled by
  clearing TE and RE bits in SCCR2 register

51
LPM Stop Mode

• Instruction Code (STOP) S bit of CCR clear
• Lowest power consumption mode
• All clocks are stopped
• Exit using RESET, XIRQ, or Unmasked IRQ

52
LPM Stop Mode

• XIRQ has two recovery methods
• X is set ? Returns to command following STOP
• X is clear ? stacking sequence that leads to
  normal XIRQ request