CS 2200 Lecture 07 Interrupts, MemoryMapped IO

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CS 2200 Lecture 07Interrupts, Memory-Mapped I/O

• (Lectures based on the work of Jay Brockman,
  Sharon Hu, Randy Katz, Peter Kogge, Bill Leahy,
  Ken MacKenzie, Richard Murphy, and Michael
  Niemier)

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Interrupts

• Whats an interrupt?
• 1 Idea an unsolicited procedure call.
• Actual procedure called an exception/trap/interrup
  t handler
• Why do we need them?
• Or put another way, what would we have to do if
  we didnt have them?

(Example constantly or periodically check
I/0, peripheral devices, etc.)
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Interrupts

• How can interrupts be generated?

?
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Interrupts

• Different Types (2200 Definitions)
• Exception - Associated with certain instruction
• Overflow
• Illegal Instruction
• Traps System calls
• Interrupt - Asynchronous event not associated
  with a certain instruction (e.g. I/O device).

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Interrupts/Exceptions/Traps
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Interrupts

• Hardware
• System bus contains 1 or more interrupt lines.
• Need to know who
• might put device type code on data lines
• might put address of table entry
• might put address of handling routine
• May have priority scheme
• What would priority be based on?
• How would it work?
• What has to happen?

i.e. what do we do, consider if interrupt is
caused by HW?
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Interrupts

• Hardware (Continued)
• Save current PC on stack
• Why the stack?
• Other possibilities?
• Go somewhere to handle interrupt
• Check each device
• Must be quick
• Interrupt vector table
• Located in low memory
• Table of pointers

(interrupt might tell CPU to go to this table
specific location is pointer to routine to
handle analogous to assembly code)
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Interrupts

• Hardware (Continued)
• What if we get interrupted in while handling
  interrupt?
• What do we do when handling interrupt is
  complete?
• Special Instruction RETI
• Can a user disable interrupts?
• followed by
• while(1)

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Interrupts

• Software
• System call (Monitor call)
• Why do we need such a construct?
• Concept of Mode
• Mode bit
• User mode
• Can execute limited instruction set
• Supervisor or Kernel or Monitor Mode
• Used by OS
• Can execute all instructions
• Switch to user mode before returning to user.

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Interrupts

• Interrupt handler code
• Like a function
• Pointed to by vector table or address supplied by
  device
• Must save state of interrupted process

(very much like a procedure call)
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Today Interrupts

• A. Running example an I/O device
• e.g., network interface
• B. Interrupt mechanics Hardware
• C. Interrupt mechanics Software (handlers)
• D. Aside CPU load of interrupts
• E. Generalizing interrupts/exceptions/traps
• and connect back to protection

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A. Running Example

• I/O Device a network interface

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Network Interface?(NI)
?
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Crude Network Interfaceinput-only

• 1. Network sends us messages need some state to
  store those messages
• 2. Need to know that messages have arrived
• 3. Need some scheme to be sure we read a message
  before the network overwrites it.

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Crude Network Interface
1. data area
DAV bit (Data AVailable bit) 2. set by
network 3. reset by software
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How to connect it?make it look like another
memory unit
could use combinational logic in control to
help check/process
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Memory-Mapped I/O

• NI is a 17-word block mapped to 0xF0000000
• Existing 1024-word memory at 0x00000000
• How do you wire up two memory units?
• hardware question
• How do you read messages from the NI?
• software question

LC-2200 address space
0xFFFFFFFF 0xF0000000 0x000003FF 0x000
00000
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Memory-Mapped Devices

• Network, disk, display, sound, keyboard, mouse
• Add data/control registers of each to addr. space
• And continuously check for input??

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B. Interrupt MechanicsHardware
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Interrupts
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Interrupts
Address Bus
Processor
Data Bus
Int
Device 1
Device 2
Add an interrupt request line. A device wishing
to interrupt asserts this line
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Interrupts
Address Bus
Processor
Data Bus
Int
Device 1
Device 2
The interrupt line is connected to the processor
control (state machine)
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Interrupts
Address Bus
Processor
Data Bus
Int
Device 1
Device 2
At the beginning of every instruction execution
sequence a check is made on the status of the
"int" line
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Interrupts
Address Bus
Processor
Data Bus
Int
Device 1
Device 2
If "int" is asserted special states can be used
to handle the interrupt
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Interrupts
Address Bus
Processor
Data Bus
Int
Inta
Device 1
Device 2
If the processor decides to handle the interrupt
it asserts the inta (interrupt acknowledege) line
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Interrupts
Address Bus
Processor
Data Bus
Int
Inta
Device 1
Device 2
If Device 1 was one of the devices asserting
"int" it receives the acknowledgement and doesn't
pass it on
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Interrupts
Address Bus
Processor
Data Bus
Int
Inta
Device 1
Device 2
If Device 1 wasn't one of the devices asserting
"int" it receives the acknowledgement and passes
it on
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Interrupts
Address Bus
Processor
Data Bus
Int
Inta
Device 1
Device 2
Assume it's Device 2 that wants to interrupt.
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Interrupts
Address Bus
Processor
Data Bus
Int
Inta
Device 1
Device 2
Now knowing that the processor is listening,
Device 2 can put the address of it's entry in the
interrupt vector table onto the data bus
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Interrupts
Memory
0x12345678 0x3579BDFA 0x12345678 0x3579BDFE
Address Bus
Processor
Data Bus
Int
Inta
Device 1
Device 2
The interrupt vector table is located in very low
memory and consists of a table of pointers to
interrupt handling routines
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Interrupts
Memory
0x12345678 0x3579BDFA 0x12345678 0x3579BDFE
Address Bus
Processor
Data Bus
Int
Inta
Device 1
Device 2
This allows the processor to jump to the code to
handle the interrupt
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Interrupts
Memory
0x12345678 0x3579BDFA 0x12345678 0x3579BDFE
Address Bus
Processor
Data Bus
Int
Inta
Device 1
Device 2
Once complete the handler executes a "return from
interrupt" instruction
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Hardware Mechanics Summary

• 1. Interrupt signal (INT)
• devices-to-CPU?
• 2. Interrupt Acknowledge (IACK)
• CPU-to-devices
• 3. Forced procedure call to interrupt handler

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Hardware Mechanics SummarySubtleties

• 1. Interrupt signal (INT)
• devices-to-CPU?
• 2. Interrupt Acknowledge (IACK)
• CPU-to-devices
• With multiple interrupts, which device goes
  first??
• 3. Forced procedure call to interrupt handler
• How do you get the address of the interrupt
  handler??
• Where do you keep the return address?
• n. potential recursion
• What if you get an interrupt while servicing an
  interrupt??

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IACK Problemone soln daisy-chain the IACK line
Address Bus
Processor
Data Bus
Int
Inta
Device 1
Device 2
Limitations? Alternatives?
If Device 1 was one of the devices asserting
"int" it receives the acknowledgement and doesn't
pass it on
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Which-Handler Problem
(i.e. how do we handle the interruption in the
CPU?)

• Options?
• 1. One handler leave dispatch to software!
• 2. Interrupt vector table
• device provides a number at IACK time
• CPU (microcode) uses number to index into a table
• CPU jumps to address in that table
• Illustrated in preceeding slides
• 3. Raw vector
• device provides an address at IACK time and CPU
  jumps
• used in Project 2

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Crude Network Interfacea la project 2
Add 18th word NIVEC pointer to interrupt
handler
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Return-Address Problem

• Standard procedure call uses JALR and saves the
  return address in register RA
• Interrupt procedure call cant use RA
• its unpredictable and would smash whatever is
  there!
• Options?
• many...
• Last time PRJ2 dedicates a processor register,
  K0

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Recursive Interrupt Problem
Memory
0x12345678 0x3579BDFA 0x12345678 0x3579BDFE
Address Bus
Processor
Data Bus
Int
Inta
Device 1
Device 2
What if Device 2 interrupts while the handler for
Device 1 is running? Or vice versa? Or double
interrupt from the same device?
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Recursive Interrupt Problem
Memory
0x12345678 0x3579BDFA 0x12345678 0x3579BDFE
Address Bus
Processor
Data Bus
Int
0
intr enable
Inta
Device 1
Device 2
Add an interrupt enable bit to the
processor 1. cleared at interrupt time 2. set
at RETI time 3. EI/DI instrs.
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C. Interrupt MechanicsSoftware

• Interrupt Handlers

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Example Device Interrupt(Say, arrival of
network message)
Save registers ? lw r1,20(r0) lw r2,0(r1) addi
r3,r0,5 sw 0(r1),r3 ? Restore registers Clear
current Int RETI
? add r1,r2,r3 subi r4,r1,4 slli
r4,r4,2 Hiccup(!) lw r2,0(r4) lw r3,4(r4) add r2
,r2,r3 sw 8(r4),r2 ?
(callee save)
External Interrupt
Interrupt Handler
code to handle int.
(callee restore)
(reset bit)
(return from interrupt)
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Interrupt Mechanisms

• Basic mechanism forced subroutine call (transfer
  of control w/saved return address)
• Must have a means to disable interrupts to
  prevent nested, recursive interrupts.
• one bit
• Additions for performance
• selective disable of multiple interrupt sources
  (priority level or a bit-per-source)
• hardware to encode the source of the interrupt.

(if another interrupt comes along, we wait or
keep trying to send)
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Nested Interrupts
(if higher priority interrupt comes along, we
could process it first)
Raise priority Reenable All Ints Save
registers ? lw r1,20(r0) lw r2,0(r1) addi
r3,r0,5 sw 0(r1),r3 ? Restore registers Clear
current Int Disable All Ints Restore priority RTE
? add r1,r2,r3 subi r4,r1,4 slli
r4,r4,2 Hiccup(!) lw r2,0(r4) lw r3,4(r4) add r2
,r2,r3 sw 8(r4),r2 ?
Could be interrupted by disk
Network Interrupt
Note that priority must be raised to avoid
recursive interrupts!
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Example Handler

• Init code
• Write to NIVEC register
• Handler code
• save all registers used by handler to stack
• do handler action
• restore all registers used by handler from stack
• JALR K0, ZERO

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D. CPU Load of Interrupts

• Interrupts cost some CPU time

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Suppose we have lots of devices
Address Bus
Processor
Data Bus
Device 37
Device 1
Device 1
Device 1
Device 1
Device 1
Device 2
All generating interrupts...
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How do you know theres enough CPU time?
Device Rate Handler time ------
---- ------------ Network 100/S
1mS Display 50/S 10mS
What fraction of the CPU is consumed by
interrupts? Could we add a sound card if it took
5mS, 100/S?
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How do you know theres enough CPU time?
Device Rate Handler time ------
---- ------------ Network 100/S
1mS --gt 10 Display 50/S
10mS --gt 50
100 int/s 1 ms/int 1s/1000ms 0.1 50 int/s
10 ms/int 1s/1000ms 0.5 100 int/s 5
ms/int 1s/1000ms 0.5
What fraction of the CPU is consumed by
interrupts? ? 60 Could we add a sound card if
it took 5mS, 100/S? ? that would be 50 ...
no!, 6050 gt 100
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E. Generalization

• Interrupts for internal events
• Interrupts as part of protection

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Interrupt/Exception/Trap Classifications

• Interrupts caused by asynchronous, outside
  events
• I/O devices requiring service (disk, network)
• Clock interrupts (real time scheduling)
• Exceptions relevant to the current instruction
• Faults, arithmetic traps, other synchronous traps
• Traps deliberately caused by the current
  instruction
• Invoke software on behalf of the currently
  executing process
• Other, e.g. hardware failure
• Non recoverable ECC, power outage, FPU is on
  fire...
• asynchronous
• not necessarily recoverable

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Interrupt/Exception/Trap Classifications

• Interrupts caused by asynchronous, outside
  events
• Exceptions synchronous but unintentional
• Traps synchronous, intentional
• HP Exceptions of which some are interrupts
• SGG Interrupts of which some are
  exceptions/traps
• occasionally seen
• fault (as in page fault ... an exception in
  our terminology)
• machine check (unrecoverably fatal condition)

WARNING Inconsistent Terminology Zone
first of several, unfortunately
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Interrupts and Protection

• Interrupts and protection are orthogonal
• However, conventionally, interrupts switch into
  supervisor (kernel) state.
• some interrupt handlers must be protected
• deliberately-invoked-traps (software traps) make
  a nice interface for system calls
• therefore, it has been convenient to have all
  interrupts go to the kernel

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Summary(note wrap-up visualization follows)

• A. I/O devices memory-map their state
• B. Interrupt mechanics Hardware
• C. Interrupt mechanics Software (handlers)
• D. CPU load of interrupts compute of time
• E. General Mechanism Interrupts/Exceptions/Traps

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Visualization of Program Execution
PC (mem. addr.)
time
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Visualization of Program Execution
a procedure call
a loop
PC (mem. addr.)
an interrupt
time
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Program Execution w/Protection
1. interrupts go to kernel mode 2. system calls
switch to kernel mode to interact w/IO
a loop
user space
PC (mem. addr.)
a system call
kernel space
an interrupt
time
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Program Execution w/Protection ( w/IO)
I/O (kernel) space
a loop
user space
PC (mem. addr.)
a system call
kernel space
an interrupt
time
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Bonus Slides

• Speed of Interrupts

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Example Device Interrupt(Say, arrival of
network message)
Raise priority Reenable All Ints Save
registers ? lw r1,20(r0) lw r2,0(r1) addi
r3,r0,5 sw 0(r1),r3 ? Restore registers Clear
current Int Disable All Ints Restore priority RTE
? add r1,r2,r3 subi r4,r1,4 slli
r4,r4,2 Hiccup(!) lw r2,0(r4) lw r3,4(r4) add r2
,r2,r3 sw 8(r4),r2 ?
External Interrupt
Interrupt Handler
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Alternative Polling(again, for arrival of
network message)
Disable Network Intr ? subi r4,r1,4 slli
r4,r4,2 lw r2,0(r4) lw r3,4(r4) add r2,r2,r3 sw
8(r4),r2 lw r1,12(r0) beq r1,no_mess lw r1,20(r0)
lw r2,0(r1) addi r3,r0,5 sw 0(r1),r3 Clear
Network Intr ?
Polling Point (check device register)
Handler
no_mess
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Delays of Interrupts/Polling

• Interrupts
• disrupts pipeline (usually must wait for a
  pipeline flush)
• save/restore registers
• other housekeeping (priority adjustments, kernel
  stuff)
• Polling
• must perform check whether theres an event
  waiting to be processed or not.
• if check is periodic, event delivery is delayed
  by half a period if events arrive at random.

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Is Polling faster or slower than Interrupts?

• Polling is faster!
• Compiler knows which registers in use at polling
  point. Hence, do not need to save and restore
  registers (or not as many).
• Other interrupt overhead avoided (pipeline flush,
  trap priorities, etc).
• Interrupts are faster!
• Overhead of polling instructions is incurred
  regardless of whether or not handler is run.
  This could add to inner-loop delay.
• Device may have to wait for service for a long
  time.
• When to use one or the other?
• Multi-axis tradeoff
• Frequent, regular events are good for polling, as
  long as the device can be controlled at user
  level.
• Interrupts are good for infrequent/irregular
  events
• Interrupts are good for ensuring predictable
  service of events.