Chapter 6

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Chapter 6 MSP430Micro-Architecture
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Concepts to Learn

• Computer Architecture
• MSP430 Micro-Architecture
• Instruction Cycle Review
• Fetch Cycle
• Addressing Modes
• Operand Fetch Cycles
• Execute Cycle
• Store Cycle
• Instruction Clock Cycles
• Digital I/O

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Levels of Transformation
Problems
Algorithms
Language (Program)
Programmable
Machine (ISA) Architecture
Computer Specific
Microarchitecture
Manufacturer Specific
Circuits
Devices
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Computer Architecture
Computer Architecture
Like a building architect, whose place at the
engineering/arts and goals/means interfaces is
seen in this diagram, a computer architect
reconciles many conflicting or competing demands.
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MSP430 Modular Architecture
MSP430 Micro-Architecture
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Memory Organization
MSP430 Micro-Architecture
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Micro-Architecture Simulator
MSP430 Micro-Architecture
Address Bus
Program Counter
Memory Address Register
Source Operand
Instruction Register
Destination Operand
Port 1 Output
Memory
Arithmetic Logic Unit
Condition Codes
Data Bus
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Quiz

• Disassemble the following MSP430 instructions

Address Data 0x8010 4031 0x8012 0600 0x8014 40B
2 0x8016 5A1E 0x8018 0120 0x801a 430E 0x801c 5
35E 0x801e F07E 0x8020 000F 0x8022 1230 0x8024
000E 0x8026 8391 0x8028 0000 0x802a 23FD 0x802
c 413F 0x802e 3FF6
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Quiz

• Disassemble the following MSP430 instructions

Address Data 0x8010 4031 0x8012 0600 0x8014 40B
2 0x8016 5A1E 0x8018 0120 0x801a 430E 0x801c 5
35E 0x801e F07E 0x8020 000F 0x8022 1230 0x8024
000E 0x8026 8391 0x8028 0000 0x802a 23FD 0x802
c 413F 0x802e 3FF6
mov.w 0x0600,r1
mov.w 0x5a1e,0x0120
mov.w 0,r14
add.b 1,r14
and.b 0x0f,r14
push 0x000e
sub.w 0,0(r1)
jne 0x8026
mov.w _at_r1,r15
jmp 0x801c
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The Instruction Cycle
Instruction Cycle

• INSTRUCTION FETCH
• Obtain the next instruction from memory
• DECODE
• Examine the instruction, and determine how to
  execute it
• SOURCE OPERAND FETCH
• Load source operand
• DESTINATION OPERAND FETCH
• Load destination operand
• EXECUTE
• Carry out the execution of the instruction
• STORE RESULT
• Store the result in the designated destination

Not all instructions require all six phases
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Fetching an Instruction
Fetch Cycle
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Addressing Modes
Addressing Modes
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Source Addressing Modes
Addressing Modes

• The MSP430 has four basic modes for the source
  address
• Rs - Register
• x(Rs) - Indexed Register
• _at_Rs - Register Indirect
• _at_Rs - Indirect Auto-increment
• In combination with registers R0-R3, three
  additional source addressing modes are available
• label - PC Relative, x(PC)
• label Absolute, x(SR)
• n Immediate, _at_PC

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MSP430 Source Constants
Addressing Modes

• To improve code efficiency, the MSP430
  "hardwires" six register/addressing mode
  combinations to commonly used source values
• 0 - R3 in register mode
• 1 - R3 in indexed mode
• 4 - R2 in indirect mode
• 2 - R3 in indirect mode
• 8 - R2 in indirect auto-increment mode
• -1 - R3 in indirect auto-increment mode
• Eliminates the need to use a memory location for
  the immediate value - commonly reduces code size
  by 30.

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Destination Addressing Modes
Addressing Modes

• There are two basic modes for the destination
  address
• Rd - Register
• x(Rd) - Indexed Register
• In combination with registers R0/R2, two
  additional destination addressing modes are
  available
• label - PC Relative, x(PC)
• label Absolute, x(SR)

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Register Addressing Mode
Operand Fetch Cycles
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Source Register Mode Rs
Operand Fetch Cycles
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Destination Register Mode Rd
Operand Fetch Cycles
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Register-Indexed Addressing Mode
Operand Fetch Cycles
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Source Indexed Mode x(Rs)
Operand Fetch Cycles
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Symbolic Addressing Mode
Operand Fetch Cycles
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Source Symbolic Mode Address
Operand Fetch Cycles
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Absolute Addressing Mode
Operand Fetch Cycles
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Source Absolute Mode Address
Operand Fetch Cycles
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Register Indirect Addressing Mode
Operand Fetch Cycles
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Source Indirect Mode _at_Rs
Operand Fetch Cycles
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Register Indirect Auto-increment
Operand Fetch Cycles
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Source Indirect Auto Mode _at_Rs
Operand Fetch Cycles
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Immediate Addressing Mode
Operand Fetch Cycles
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Source Immediate Mode n
Operand Fetch Cycles
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Execute Phase PUSH.W
Execute Cycle
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Execute Phase Jump
Execute Cycle
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Store Phase Rd
Store Cycle
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Store Phase Other
Store Cycle
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Instruction Timing
Instruction Clock Cycles

• Instruction cycles Power consumption
• Most instruction cycles limited by access to
  memory (von Neumann bottleneck)
• In general
• 1 cycle to fetch instruction
• 1 cycle for _at_Rn, _at_Rn, or immediate
• 2 cycles for indexed, absolute, or symbolic
• 1 to write destination back to memory
• 2 cycles for any jump
• No difference between byte and word

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Digital I/O
Digital I/O

• Digital I/O grouped in 8 bit memory locations
  called ports
• Each I/O port can be
• programmed independently for each bit
• combined for input, output, and interrupt
  functionality
• Edge-selectable input interrupt capability for
  all 8 bits of ports P1 and P2
• Read/write access using regular MSP430 byte
  instructions
• Individually programmable pull-up/pull-down
  resistors
• The available digital I/O pins for the hardware
  development tools
• eZ430-F2013 10 pins - P1 (8 bits) and P2 (2
  bits)
• eZ430-F2274 32 pins P1, P2, P3, and P4

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8-bit Digital I/O Registers
Digital I/O

• Direction Register (PxDIR)
• Bit 1 the individual port pin is set as an
  output
• Bit 0 the individual port pin is set as an
  input
• Input Register (PxIN)
• When pins are configured as GPIO, each bit of
  these read-only registers reflects the input
  signal at the corresponding I/O pin
• Bit 1 The input is high
• Bit 0 The input is low
• Output Register (PxOUT)
• Each bit of these registers reflects the value
  written to the corresponding output pin.
• Bit 1 The output is high
• Bit 0 The output is low.
• Note the PxOUT is a read-write register which
  means previously written values can be read,
  modified, and written back

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Select Digital I/O Registers
Digital I/O

• Function Select Registers (PxSEL) and (PxSEL2)

PxSEL PxSEL2 Pin Function
0 0 Selects general purpose I/O function
0 1 Selects the primary peripheral module function
1 0 Reserved (See device-specific data sheet)
1 1 Selects the secondary peripheral module function

• Port P2.0 Example

P2SEL.0 ADC10AE0.0 Pin Function
0 0 General-purpose digital I/O pin
1 0 ACLK output
X 1 ADC10, analog input A0 / OA0, analog input I0
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Interrupt Digital I/O Registers
Digital I/O

• Interrupt Enable (PxIE)
• Read-write register to enable interrupts on
  individual pins on ports P1/P2
• Bit 1 The interrupt is enabled
• Bit 0 The interrupt is disabled
• Each PxIE bit enables the interrupt request
  associated with the corresponding PxIFG interrupt
  flag
• Interrupt Edge Select Registers (PxIES)
• Selects the transition on which an interrupt
  occurs
• Bit 1 Interrupt flag is set on a high-to-low
  transition
• Bit 0 Interrupt flag is set on a low-to-high
  transition
• Interrupt Flag Registers (PxIFG)
• Set automatically when the programmed signal
  transition (edge) occurs
• PxIFG flag can be set and must be reset by
  software
• Bit 0 No interrupt is pending
• Bit 1 An interrupt is pending

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Pull-up/down Register
Digital I/O

• Pull-up/down Resistor Enable Registers (PxREN)
• Each bit of this register enables or disables the
  pull-up/pull-down resistor of the corresponding
  I/O pin
• Bit 1 Pull-up/pull-down resistor enabled
• Bit 0 Pull-up/pull-down resistor disabled.
• When pull-up/pull-down resistor is enabled,
  Output Register (PxOUT) selects
• Bit 1 The pin is pulled up
• Bit 0 The pin is pulled down.

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Port P1 Registers
Digital I/O
Register Name Short Form Address Register Type Initial State
Input P1IN 020h Read only -
Output P1OUT 021h Read/write Unchanged
Direction P1DIR 022h Read/write Reset with PUC
Interrupt Flag P1IFG 023h Read/write Reset with PUC
Interrupt Edge Select P1IES 024h Read/write Unchanged
Interrupt Enable P1IE 025h Read/write Reset with PUC
Port Select P1SEL 026h Read/write Reset with PUC
Port Select 2 P1SEL2 041h Read/write Reset with PUC
Resistor Enable P1REN 027h Read/write Reset with PUC
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