ECE3120: Computer Systems Chapter 6: Interrupts Dr. Xubin He

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ECE3120 Computer SystemsChapter 6 Interrupts

• Dr. Xubin He
• http//iweb.tntech.edu/hexb
• Email hexb_at_tntech.edu
• Tel [phone], Brown Hall 319

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• Prev
• Concepts of Interrupts
• Today
• 68HCS12 Exceptions

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• 68HCS12 Exceptions
• Maskable interrupts including IRQ pin and all
  peripheral function interrupts.
• Nonmaskable interrupts including XIRQ pin, SWI
  interrupt, and
• unimplemented opcode trap.
• Resets including the power-on reset, reset pin
  manual reset, the COP reset
• (computer operate properly), and clock monitor
  reset.
• Maskable Interrupts
• Different 68HCS12 members implement different
  number and types of peripheral functions, and
  hence may have different number of maskable
  interrupts.
• One of the maskable interrupts can be raised to
  the highest priority among the maskable
  interrupt group and receive quicker service. This
  is achieved by
• programming the HPRIO register.

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To raise a maskable interrupt source to the
highest priority, write the low byte of the
vector address of this interrupt to the HPRIO
register. Exceptions that have higher vector
addresses are at higher priorities.
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• IRQ Pin Interrupt
• The only external maskable interrupt for the
  HCS12.
• IRQ interrupt can be edge-triggered or
  level-triggered.
• IRQ interrupt has a local enable mask in the
  IRQCR register.
• The IRQ interrupt is configured by programming
  the IRQCR register.
• The contents of the IRQCR register are shown in
  Figure 6.2.

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Making IRQ Level-Sensitive Pros Multiple
interrupt sources can be tied to this
pin. Cons Need to make sure that the IRQ signal
has become inactive before the IRQ service
routine is complete if there is only one
interrupt request pending. Making IRQ
Edge-Sensitive Pros No need to control the
duration of the IRQ pulse. Cons Not suitable
for noisy environment because every falling edge
caused by noise will be recognized as an
interrupt. When does the MCU recognize interrupt
requests? The MCU recognizes the interrupt
request when it completes the execution of the
current instruction unless the current
instruction is a fuzzy logic instruction. For
fuzzy logic instructions, the HCS12 recognizes
the interrupt immediately.
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• The Stack Order on Entry of an Interrupt
• The 68HCS12 saves all CPU registers on an
  interrupt.
• The order of saving CPU registers is shown in
  Figure 6.3.

• The RTI Instruction
• RTI is used to terminate interrupt service
  routines.
• RTI will restore CPU registers from the stack.
• The 68HCS12 will continue to execute the
  interrupted program unless there is
• another pending interrupt.

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Nonmaskable Interrupts

• There are three nonmaskable interrupts XIRQ pin,
  SWI instruction, and unimplemented instruction
  opcode trap.
• XIRQ Pin Interrupt
• XIRQ interrupt is disabled during a system
  reset and upon entering the service routine of
  another XIRQ interrupt.
• After minimal system initialization, software
  can clear the X bit of the CCR register to enable
  the (using the andcc BF instruction) XIRQ
  interrupt. Software cannot reset the X bit once
  it has been set.
• When a nonmaskable interrupt is recognized,
  both the X and I bits are set after CPU registers
  are saved.
• The execution of an RTI instruction at the end
  of the XIRQ service routine will restore the X
  and I bits to the pre-interrupt request state.
• Unimplemented Opcode Trap
• There are 202 unimplemented opcode on page 2
  (16-bit opcode).
• These unimplemented opcode share the same
  vector FFF8FFF9.
• Software Interrupt Instruction (SWI)
• Execution of the SWI instruction causes an
  interrupt without an interrupt request signal.
• The SWI instruction is commonly used in the
  debug monitor to implement
• breakpoints and to transfer control from a user
  program to the debug monitor.
• A breakpoint in a user program is a memory
  location where we want program execution to be
  stopped and information about instruction
  execution (in the form of register contents) to
  be displayed.

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Interrupts in D-Bug12 EVB Mode

• On-chip flash memory locations are not available
  for user to store interrupt vectors.
• D-Bug12 monitor provides SRAM-based interrupt
  vector table.
• The SRAM-based table (in Table 6.3) starts at
  3E00 and has 64 entries.
• The interrupt SCI0 has been used by the monitor
  and is not available to the user.
• Mnemonic names are defined for users to store
  their interrupt vectors in the table. Both the
  hcs12.inc and the vectors12.h (for C language)
  have the definitions for these entries.

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Setting Up the Interrupt Vector

• The label (or name) of the IRQ interrupt service
  routine is IRQISR.
• In assembly language
• movw IRQISR,UserIRQ store the vector at the
  designated address

• Example 6.1
• The IRQ pin of the HCS12DP256 is connected to a
  1-Hz digital waveform and port B is connected to
  eight LEDs. Write a program to configure port B
  for output and enable the IRQ interrupt and also
  write the service routine for the IRQ interrupt.
• The service routine for the IRQ interrupt simply
  increments a counter and outputs it to port B.
• Solution
• Next slide

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include "c\miniide\hcs12.inc" org 1000 count d
s.b 1 reserve one byte for count org 1500 ld
s 1500 set up the stack pointer movw IRQISR
,UserIRQ set up interrupt vector in
SRAM clr count movb FF,DDRB configure port
B for output bset DDRJ,02 configure PJ1 pin
for output (required in Dragon12) bclr PTJ,02
enable LEDs to light (required in
Dragon12) movb count,PTB display the count
value on LEDs movb C0,IRQCR enable IRQ pin
interrupt, select edge-triggering cli
" forever nop bra forever wait for IRQ pin
interrupt
This is
the IRQ service routine.

IRQISR inc count increment
count movb count,PTB and display count on
LEDs rti end
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Real-time interrupt (RTI) (1 of 3)

• Main function is to generate periodic interrupt
  to the MCU.
• The RTI is enabled by the CRGINT register (shown
  in Figure 6.11).
• The interrupt interval of RTI is selected by the
  RTICTL register (shown in Figure 6.16).
• The actual available interrupt periods for RTI
  are listed in Table 6.4.

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RTI (2 of 3)
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RTI (3 of 3)
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Resets

• There are four possible sources of resets
• Power-on reset (POR)
• External reset (RESET pin)
• COP (computer operate properly) reset
• Clock monitor reset

• Power-On Reset
• The 68HCS12 has circuitry to detect a positive
  transition in the VDD supply and initialize the
  microcontroller by asserting the reset signal
  internally.
• The reset signal is released after a delay that
  allows the device clock generator to stabilize.
• External Reset (RESET pin)
• The 68HCS12 has circuit to distinguish internal
  and external resets.
• The on-chip EEPROM may be corrupted if the
  power supply drops below the required level. When
  the power supply drops below the required level,
  the RESET signal should be pulled low to prevent
  instruction execution.
• - A low-voltage inhibit circuit such as the
  Motorola MC34064 can be used to protect against
  the EEPROM corruption. Figure 6.4 shows an
  example of reset circuit and LVI circuit.

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• COP Reset
• The computer operate properly (COP) system is
  designed to protect against
• software failure.
• If software was written correctly, it should
  follow certain sequence of execution and the
  execution time can also be predicted.
• When the COP is enabled, software must write
  55 and AA (in this order) to the COPRST
  register to keep a watchdog timer from timing
  out.
• If our software was not written properly, then
  it may not write 55 and AA to the COPRST
  (located at 17) before the COP times out and the
  CPU will be reset. The software problems can
  therefore be detected.
• The operation of the COP timer circuit is
  configured by the COPCTL register. The contents
  of the COPCTL register are shown in Figure 6.5.
• The COP system is driven by a constant
  frequency of E/213. The bits 2, 1, and 0 specify
  an additional division factor to arrive at the
  COP timeout rate.

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• Clock Monitor Reset
• The clock monitor reset circuit uses an internal
  RC circuit to determine whether the clock
  frequency is above a predetermined limit.
• If no EXTALi clock edges are detected within
  this time delay, the clock
• monitor can optionally generate a system reset.
• The clock monitor function is enabled/disabled
  by the CME control bit in the COPCTL register.
  Clock monitor time-outs are shown in Table 6.3.

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HCS12 Operation Modes

• The HCS12 can operate in eight different
  operation modes (shown in Table 6.5).
• The states of BKGD, MODB, and MODA pins are
  latched to determine the MCU operation modes.
• Expanded modes allow the user to access external
  memory where single chip modes do not.
• In expanded modes, Port A and B become the
  time-multiplexed address and data port.

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Normal Operation Modes
Normal Expanded Wide Mode Ports A and B are used
as 16-bit address and data buses. ADDR15..8 and
DATA15..8 are multiplexed on port A. ADDR7..0
and DATA7..0 are multiplexed on port B.
Normal Expanded Narrow Mode The 16-bit
external address bus uses port A for the high
byte and port B for the low byte. The 8-bit
external data bus uses port A. ADDR15..8 and
DATA7..0 are multiplexed on port A. Normal
Single-Chip Mode Normal single-chip mode has no
external buses. The 68HC12 cannot access external
memory in this mode.
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Special Operation Modes
Special Expanded Wide Mode This mode is for
emulation of normal expanded wide mode and
emulation of normal single-chip mode with a
16-bit bus. The bus-control pins of port E are
all configured for their bus-control output
functions rather than general-purpose
I/O. Special Expanded Narrow Mode This mode is
for emulation of normal expanded narrow mode.
External 16-bit data is handled as two
back-to-back bus cycles, one for the high byte
followed by one for the low byte. Internal
operations continue to use full 16-bit data
paths. Special Single Chip Mode a) The CPU is
forced to active background debug mode to allow
system debugging through the BKGD pin. b) The
BDM takes control of the CPU and is waiting for
additional serial commands through the BKGD
pin. c) There are no external address and data
buses. Special Peripheral Mode a) The CPU is not
active. b) An external master can take control
on-chip peripherals for testing
purposes. c) Background debugging should not be
performed in this mode
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Next

• Chapter 8 Timer