Imaging pixel matrices with 3D readout

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Imaging pixel matrices with 3D readout

• Trento, February 13 2006 / S. Eränen

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• Partners
• Oxford Instruments Analytical (Seppo Nenonen,
  Hans Andersson, Veikko Kämäräinen)
• Detection Technology (Mikko Juntunen, Ji Fan)
• VTT (Tuula Virolainen, Ismo Luusua, Kimmo
  Henttinen, Hannu Luoto, Juha Kalliopuska, Simo
  Eränen)
• TEKES

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OUTLINE

• 1. DEVICE BENEFITS
• 2. PROCESS
• SUBSTRATES
• PROCESS FLOW (VIA FIRST / DIODE FIRST)
• 3. STRUCTURES
• VIA RESISTANCE CONTACT RESISTANCE INSULATION
• I/O DISTANCE
• PIXEL MATRIX
• 4. RESULTS SIMULATIONS
• SIMULATIONS
• SEMs
• VIA RESISTANCE CONTACT RESISTANCE
• LEAKAGE VIA DISTANCE BLOCKING
• REAL DEVICES
• 5. CHALLENGES CONCLUSIONS

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1. DEVICE BENEFITS

• CONSIDER ONE PIXEL OF IMAGING MATRIX (PD)

bulk Si
anode
oxide
Al
cathode
poly
BENEFITS

• reduced area for read-out lines ? large area
  devices
• constant pixel capacitance
• mechanical FC or CSP joining of optical sensors
  ? detector tiles ? large area imaging systems

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2. PROCESS

• SUBSTRATES
• several substrates including FZ ( gt 6 kohmcm)
• wafer thickness 400 mm

• PROCESS FLOW (via first)
• field oxide
• icp hard mask 1st mask
• deep silicon etching
• via isolation
• via filling (poly silicon)
• planarization
• p-type anode 2nd mask
• backside implantation 3rd mask
• activation
• contact windows (front/back) 4th 5th masks

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PROCESS FLOW (continued)

• metal (Al) pattern (front/back) 6th 7th masks
• passivation (oxide)
• passivation windows (front/back) 8th 9th masks
• anneal
• UBM (depending on solder metallurgy) 10th mask

S 10 MASKS, DSP COMPLEXITY 3D
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3. GENERIC STRUCTURES
(A) VIA RESISTANCE INSULATION CONTACT
RESISTANCE
Kelvin bridge
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(B) I/O DISTANCE
SIMILAR STRUCTURES WITHOUT GUARD RING
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(C) PIXEL MATRIX
pitch 200 mm
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4. RESULTS
(A) SIMULATIONS
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(A) SIMULATIONS
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(A) SIMULATIONS
t 10-5 s
VBD gt 200 V
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(B) SEMs
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(C) VIA RESISTANCE CONTACT RESISTANCE
Rvia 400700 ohm
rpoly gt 100 mohmcm Ndoping lt 31017 cm-3
Rc lt 50 mohm for 48 mm2 contact window
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(D) LEAKAGE VIA ISOLATION VIA DISTANCE
anode area 1 mm2

• SHORT VIA ANODE DISTANCE ALLOWED
• BREAKDOWN gt 200 V
• VIA ISOLATION gt 200 V _at_ 1 nA

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(E) REAL DEVICES
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(F) REAL DEVICES

• LEAKING DEAD PIXELS SEVERAL FAILURE MODES

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5. CONCLUSION CHALLENGES

• APPROACH FEASIBLE
• SHORT VIA-ANODE DISTANCE ALLOWED
• PRODUCTIONAL PROCESS NEEDED ( ICP / FILLING /
  PLANARIZATION)
• PIXEL YIELD ( SEVERAL FAILURE MODES)
• PIXEL PITCH SCALING