Digital Integrated Circuits

1
Digital Integrated Circuits

• Flip-flops and Counters
• PHYS 333 334 LAB-D2

2
Review
1
Clocked RS Flip Flop C0 disables FF to avoid
indeterminate state (S,R)(1,1)
0
1
1
D Flip Flop inverter eliminates (1,1) state
1
0
3
JK Flip Flop
CLEAR (RD)
Negative or Falling Edge
Active Low
Clock
time
CLOCK (CP)
74LS73 - Dual Negative Edge-Triggered J-K
Flip-Flop with Clear
4
JK Flip Flop
Timing diagram
Function Table
J
J
K
C
Q
K
1
0
1
C
0
1
0
Q
1
Qn1 Qn
1
J 0 K 1 RESET
J 1 K 1 TOGGLE
J 0 K 0 NC
J 1 K 1 TOGGLE
J 1 K 0 SET
0
0
No change
Toggle (ie /2)
Useful for counting
5
74LS73
Pin diagram
6
Single Pulse Clock (switch debouncer)
Vout
5 V
Logic Switch
5
Vout
o
o
time
msec
RS latch
5V
1
1k
0
Wire
Falling edge of clock
1
1
1
S1
2
Single Pulse
S1 at 2 ? CLK 1 (LED on) S1 at 1 ? CLK 0
(LED off)
0
1
0
1k
330
Debounced Switch
7
Experimental Work

• Build the logic circuit
• Verify the truth table using single clock pulse
• Observe the toggle state (i.e. JK1)
• Observe that the negative edge of the clock (ie
  ) changes Q

Fig D2.2
J
8
Experimental Work contd

• Sketch Q (from oscilloscope) on the timing
  diagram using 100KHz TTL pulses as the clock.
  Use toggle state (JK1)

To oscilloscope
J
100KHz Clock, TTL From signal generator
9
4-bit Binary Ripple Counter

• Build the ripple counter using the 7493
  (connections shown below)
• Note JK flip flops are connected internally in
  toggle State (i.e. divide by 2)
• Check it works with 1 Hz TTL Clock
• Complete the truth table
• Sketch (from oscilloscope) on the timing diagram
  20, 21, 22, 23 signals over 16 clock
• pulses using 100KHz TTL clock.

10
Binary Ripple Counter Truth Table
MSB
LSB"
11
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