Digital Integrated Circuits A Design Perspective

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Digital Integrated CircuitsA Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje
Nikolic
Designing CombinationalLogic Circuits
April 6, 2004
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Pass-TransistorLogic
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Class Information

• Makeup Quiz is on Thu. 4/8/04. Worth 10
  points.Purpose to make-up for test1 loss of 10
  pts.Any test1 like question is fair
  game10-15 minute duration
• Project part 1 is due next week!
• Anyone looking for a partner?

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Schedule
QUIZ
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Pass-Transistor Logic
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Example AND Gate
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NMOS-Only Logic
3.0
In
Out
2.0
V
x

e
g
a
t
l
o
V
1.0
0.0
0
0.5
1
1.5
2
Time ns
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NMOS-only Switch
V
C
2.5 V
C
2.5

M
2
A
2.5 V
B
A
2.5 V
M
n
B
M
C
1
L
does not pull up to 2.5V, but 2.5V -
V
V
TN
B
Threshold voltage loss causes
static power consumption
NMOS has higher threshold than PMOS (body effect)
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NMOS Only Logic Level Restoring Transistor
V
DD
V
DD
Level Restorer
M
r
B
M
2
X
M
A
Out
n
M
1
Advantage Full Swing
Restorer adds capacitance, takes away pull down
current at X
Ratio problem
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Restorer Sizing
3.0

• Upper limit on restorer size
• Pass-transistor pull-downcan have several
  transistors in stack

W
/
L
1.75/0.25
V
r
e
W
/
L
1.50/0.25
g
r
a
t
l
o
V
W
/
L
1.25/0.25
W
/
L
1.0/0.25
r
r
Time ps
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Solution 2 Single Transistor Pass Gate with VT0
V
DD
V
DD
0V
2.5V
Out
0V
V
DD
2.5V
WATCH OUT FOR LEAKAGE CURRENTS
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Complementary Pass Transistor Logic
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Solution 3 Transmission Gate
C
C
A
A
B
B
C
C
C
2.5 V
A
2.5 V
B
C
L
C

0 V
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Resistance of Transmission Gate
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Pass-Transistor Based Multiplexer
S
VDD
GND
In1
In2
S
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Transmission Gate XOR
B
B
M2
A
A
F
M1
M3/M4
B
B
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Delay in Transmission Gate Networks
m
R
R
R
eq
eq
eq
In
C
C
C
C
(c)
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Delay Optimization
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Transmission Gate Full Adder
Similar delays for sum and carry
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