Concurrency and Verification

1
Concurrency and Verification

• What?
• Why?
• How?

2
What?

• Validation and Verification
• of
• software and hardware DESIGNS!
• (E.g., real time systems, embedded systems,
• communication protocols)

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A REAL real time system
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Embedded Systems
SyncMaster 17GLsi
Mobile Phone
Telephone
Digital Watch
Tamagotchi
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Why?

• Testing/simulation of designs/implementations may
  not reveal error
• Formal verification (exhaustive testing) of
  design provides 100 coverage
• TOOL support.

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Tools
Applications
MONA
UPPAAL
SPIN
PVS
HOL
ALF
TLP

• Semantics
• Concurrency Theory
• Abstract Interpretation
• Compositionality
• Models for real-time
• hybrid systems

• Algorithmic
• (Timed) Automata Theory
• Graph Theory
• BDDs
• Polyhedra Manipulation

• Logic
• Temporal Logic
• Modal Logic
• MSOL

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Model Checking
System Description A
No! Debugging Information
TOOL
Yes, Prototypes Executable Code Test
sequences
Requirement F
Tools UPPAAL, CPN, SPIN,
VisualSTATE, Statemate, Verilog,
Formalcheck,...
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System Description

• Unified Model State Machine!

y!
b?
a
Output ports
x
Input ports
b?
y
b
a?
x!
Control states
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Train Simulator
VVS visualSTATE
1421 machines 11102 transitions 2981 inputs 2667
outputs 3204 local states Declare state sp.
10476
BUGS ?
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State Explosion problem
M2
M1
a
1
2
c
b
4
3
M1 x M2
1,a
4,a
1,b
2,b
1,c
2,c
3,a
4,a
3,b
4,b
3,c
4,c
All combinations exponential in no. of
components
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Intelligent Light Control
press?
Off
Light
Bright
press?
press?
press?
WANT if press is issued twice quickly then
the light will get brighter otherwise the light
is turned off.
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Intelligent Light Control
press?
Xlt3
Off
Light
Bright
X0
press?
press?
press?
Xgt3
Solution Add real-valued clock x
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Timed Automata
Alur Dill 1990
Clocks x, y
Guard Boolean combination of comp with integer
bounds
n
Reset Action perfomed on clocks
Action used for synchronization
xlt5 ygt3
State ( location , xv , yu ) where v,u are
in R
a
Transitions
x 0
a
( n , x2.4 , y3.1415 )
( m , x0 , y3.1415 )
m
e(1.1)
( n , x2.4 , y3.1415 )
( n , x3.5 , y4.2415 )
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Model Checking
System Description A
No! Debugging Information
TOOL
Yes, Prototypes Executable Code Test
sequences
Requirement F
Tools UPPAAL, CPN, SPIN,
VisualSTATE, Statemate, Verilog,
Formalcheck,...
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Computation Tree Logic, CTLClarke Emerson 1980
Syntax
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TCTL CTL Time
E f U f , A f U f - like in CTL No EX f
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Infinite State Space?
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Regions

• Alur Dill A Theory of Timed Automata, TCS 126,
  183 - 235, 1994
• Berthomieu Menasche An Enumerative Approach
  for Analyzing Timed Petri Nets, Information
  Processing 83, 1983
• Berthomieu Diaz Modelling and Verification of
  Time Dependent Systems Using Time Petri Nets,
  IEEE Trans. on Soft. Eng. 17 (3), 1991

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Roughly speaking....
Model checking a timed automata against a
TCTL-formula amounts to model checking its
region graph against a CTL-formula
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Complexity
However Ssys may be EXPONENTIAL in number of
parallel components! -- FIXPOINT COMPUTATIONS may
be carried out using ROBDDs (Reduced
Ordered Binary Decision Diagrams) Bryant, 86
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Problem to be solved
?
?
?
Model Checking TCTL is PSPACE-hard
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Research opportunities

• Industrial Applications
• Applications to Communication Protocols
• Application Area for Algorithmics
• Concrete Projects
• Verification -gt Testing
• Specifications with local modalities

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Course material

• Joost-Pieter Katoen
• Concepts, Algorithms, and Tools

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Course structure

• Student presentations
• Brief overview of main contents
• Critical assessment
• Examples, applications
• Follow-up on literature
• Selection and solutions to exercises

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Student presentations

• 1. Linear temporal logic, PLTL (47--66)
• 2. PLTL model checking (66--124)
• 3. Computation tree logic, CTL (127--186)
• 4. Real-time CTL, TCTL (189--253)
• 5. State-space reduction (257--290)