DC Biasing BJTs

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DC Biasing - BJTs

• CHAPTER 4

2
Introduction

• BJTs amplifier requires a knowledge of both the
  DC analysis (large signal) and AC analysis (small
  signal).
• For a DC analysis a transistor is controlled by
  a number of factors including the range of
  possible operating points.
• Once the desired DC current and voltage levels
  have been
• defined, a network must be constructed that
  will establish the
• desired operating point.
• BJT need to be operate in active region used as
  amplifier.
• The cutoff and saturation region used as a
  switches.
• For the BJTs to be biased in its linear or
  active operating
• region the following must be true
• a) BE junction ? forward biased, 0.6 or 0.7V
• b) BC junction ? reverse biased

3
Introduction

• DC bias analysis ? assume all capacitors are open
  cct.
• AC bias analysis
• 1) Neglecting all of DC sources
• 2) Assume coupling capacitors are short cct.
  The effect of these capacitors is to set a
  lower cut-off frequency for the cct.
• 3) Inspect the cct (replace BJTs with its small
  signal model).
• 4) Solve for voltage and current transfer
  function and i/o and o/p impedances.
• For transistor amplifiers the resulting DC
  current and voltage establish an operating point
  that define the region that can be employed for
  amplification process.

4
Introduction

• Important basic relationships for a transistor
• VBE0.7V
• IE(ß1)IBIC
• IC ßIB

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Operating Point

• For transistor amplifiers the resulting dc
  current and voltage establish an operating point
  on the characteristics that define the region
  that will be employed for amplification of the
  applied signal.
• Operating point ? quiescent point or Q-point
• The biasing circuit can be designed to set the
  device operation at any of these points or others
  within the active region.
• The BJT device could be biased to operate outside
  the max limits, but the result of such operation
  would be shortening of the lifetime of the device
  or destruction of the device.
• The chosen Q-point often depends on the intended
  use of the circuit.

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Various operating points within the limits of
operation of a transistor

• Q-point C
• Concern on
• nonlinearities due to IB
• curves is rapidly changes
• in this region.

• Q-point B
• The best operating point
• for linear gain and largest
• possible voltage and current
• It is a desired condition for
• a small signal analysis

• Q-point A
• I0A, V0V
• Not suitable for
• transistor to operate

7
Fixed-Bias Circuit

• For the dc analysis the network can be isolated
  from the indicated ac levels by replacing the
  capacitors with an open-circuit equivalent
  because the reactance of a capacitor for dc is 8?
  
• The dc supply Vcc can be separated into two
  supplies

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Forward Bias of Base-Emitter

• Write KVL equation in the clockwise direction of
  the loop
• VCC IBRB VBE 0
• Solving the equation for the current IB results

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Collector-Emitter Loop

• The magnitude of the IC is related directly to IB
  through
• ICßIB
• Apply KVL in the clockwise direction around the
  indicated close loop results
• VCEICRC-VCC0
• VCE VCC-ICRC
• Recall that
• VCE VC - VE
• In this case, VE 0V, so
• VCEVC
• VBEVB-VE
• Than VE0V, VBEVE

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Example
Determine the following for the fixed bias
configuration a) IBQ and ICQ b) VCEQ
c) VB and VC d) VBC
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Solution
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Example
Determine the following for the fixed bias
configuration a) IBQ and ICQ b) VCEQ
c) VB d)VC e) VE
13
Solution
14
Transistor Saturation

• The term saturation is applied to any system
  where levels have reached their max values.
• For a transistor operating in the saturation
  region, the current is maximum value for a
  particular design.
• Saturation region are normally avoided because
  the B-C junction is no longer reverse-biased and
  the output amplified signal will be distorted.

The saturation current for the fixed bias
configuration is
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Example

• By refering to example 1 and the figure,
  determine the saturation level.
• Solution

16
Example

• Find the saturation current for the fixed-bias
  configuration of figure example 2.
• Solution

17
Load-Line Analysis

• We investigate how the network parameters define
  the possible range of Q-points and how the actual
  Q-point is determined.
• Refer to figure below (output loop) one straight
  line can be draw at output characteristics. This
  line is called load line.
• This line connecting each separate of Q-point.
• At any point along the load line, values of IB,
  IC and VCE can be picked off the graph.
• The process to plot the load line as follows

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Load-Line Analysis

• Step 1
• Refer to circuit, VCEVCC ICRC (1)
• Choose IC0 mA. Subtitute into (1), we get
• VCEVCC (2) ? located at X axis
• Step 2
• Choose VCE0V and subtitute into (1), we get
• ICVCC/RC (3) ? located at Y-axis
• Step 3
• Joining two points defined by (2) (3), we get
  straight line that can be drawn as Fig. 5.6.

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Load-Line Analysis
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Load-Line Analysis

• Case 1
• Level IB changed by varying the value of RB.
• Q-point moves up and down

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Load-Line Analysis

• Case 2
• VCC fixed and RC change the load line will shift
  as shown in Fig 5.8
• IB fixed, the Q-point will move as shown in the
  same figure.

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• Case 3
• RC fixed and VCC varied,
• the load line shifts as
• shown in Fig. 5.9

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Example

• Given the load line of Fig. 5.10 and defined
  Q-point, determine the
• required values of VCE, RC and RB for a fixed
  bias configuration.

IB17 uA
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Solution
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Example

• Determine the value of Q-point for this figure.
  Also find the new value
• of Q-point if ? change to 150.

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Solution
The change of ?? cause the big change of Q-point
value. This shows that fixed biased configuration
is NOT stable
ICQ VCEQ
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Emitter Bias

• The DC bias network below contains an emitter
  resistor to improve the stability level of
  fixed-bias configuration.
• The analysis consists of two scope
• - Examining the base-emitter loop (input loop)
• - Use the result to investigate the
  collector-emitter loop (output loop)

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Base-Emitter Loop
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Collector-Emitter Loop
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Example

• For the emitter-bias network fo Fig.5.14
  determine
• a)IB b)IC c)VCE d)VC e)VE
  f)VB g)VBC

Beta50
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Solution
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Saturation Level
The saturation current for an emitter-bias
configuration is
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Example
Determine the saturation current for the network
of example 7. Solution ? This value is
about three times the level of ICQ (2.01mA? ?50)
for the example 7. Its indicate the parameter
that been used in example 7 can be use in
analysis of emitter bias network.
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Load-Line Analysis
The process to plot the load line as
follows Step 1 Refer to fig. 5.13, VCEVCC
IC(RCRE) (1) Choose IC0 mA. Subtitute into (1),
we get VCEVCC (2) ? located at X axis Step
2 Choose VCE0V, subtitute into (1) gives
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Load-Line Analysis
Step 3 Joining two points defined by (2)
(3), we get straight line that can be drawn as
Fig. 5.17
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Voltage Divider Bias

• ICQ and VCEQ from the table is changing
  dependently the changing of ?.
• The voltage-divider bias configuration is
  designed to have a less dependent or independent
  of the ?.
• If the circuit parameter are properly chosen, the
  resulting levels of ICQ and VCEQ can be almost
  totally independent of ?.

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Voltage Divider Bias

• Two method for analyzed the voltage-divider bias
  configuration
• - Exact method
• - Approximate method

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Exact Analysis

• Step 1
• The input side of the network can be redrawn for
  DC analysis.
• Step 2
• Analysis of Thevenin equivalent network to the
  left of base terminal

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Exact Analysis

• Step 2(a)
• Replaced the voltage sources with short-circuit
  equivalent and gives the value of RTH

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Exact Analysis

• Step 2(b)
• Determining the ETH by replaced back the voltage
  sources and open circuit Thevenin voltage. Then
  apply the voltage-divider rule.

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Exact Analysis

• Step 3
• The Thevenin network is then redrawn and IBQ can
  be determined by KVL

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Example

• Determine the DC bias voltage VCE and current IC
  for the
• voltage-divider configuration of network below

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Solution
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Example

• For the voltage-divider bias configuration,
  determine IBQ, ICQ, VCEQ, VC, VE and VB.

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Solution
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Approximate Analysis

• Step 1
• ?RE ? 10R2
• Step 2
• The input section can be represented by the
  network of figure below and R2 can be considered
  in series by assuming
• I1?I2 and IB 0A .

This eqn must be satisfied. If not, approximate
analysis cant be used , and you have to use the
exact analysis (Thevenins method)
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Approximate Analysis

• Step 3

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NPN Transistor Simulation
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Example

• Repeat the analysis of example 9 using the
  approximate technique and compare solution for
  ICQ and VCEQ.
• Solution

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Solution
ICQ and VCEQ are certainly close.
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Example

• Repeat the exact analysis of example 9 if ? is
  reduced to 70. Compare the solution for ICQ and
  VCEQ.
• Solution

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Solution (continued)
Conclusion Even though ? is drastically half,
the level ICQ and VCEQ are essentially same.
53
Example
Determine the levels of ICQ and VCEQ for the
voltage-divider configuration using the exact and
approximate analysis. Compare the solution.
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Solution
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Solution (continued)
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Solution (continued)
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The saturation collector-emitter circuit for the
voltage-divider configuration has the same
appearance as the emitter-biased configuration as
shown below.
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Load Line Analysis
The similarities with the output circuit of the
emitter-biased configuration result in the same
intersections for the load line of the
voltage-divider configuration. The load line
therefore have the same appearance with
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DC Bias with Voltage Feedback
Another way to improve the stability of a bias
circuit is to add a feedback path from collector
to base. In this bias circuit the Q-point is only
slightly dependent on the transistor Beta ?.
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Base-Emitter Loop
Applying Kirchoffs voltage law VCC IC?RC
IBRB VBE IERE 0 Note IC? IC IB -- but
usually IB ltlt IC ? so IC? ? IC Knowing IC ?IB
and IE ? IC then VCC ?IB RC IBRB VBE
?IBRE 0 Simplifying and solving for IB

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Collector-Emitter Loop
Applying Kirchoffs voltage law IE VCE
IC?RC VCC 0 Since IC? ? IC and IC ?IB
IC(RC RE) VCE VCC 0 Solving for VCE
VCE VCC- IC(RCRE)
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Transistor Saturation Level
Load Line Analysis
It is the same analysis as for the voltage
divider bias and the emitter-biased circuits.
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Simulation of a NPN type common-emitter transistor
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Miscellaneous configuration
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Design Operation

• We are able to design the transistor circuit
  using the ideas that we have learnt before during
  analyzing dc biasing circuit.
• How?
• - Understand the Kirchoffs Law and other
  electric circuit law such as Ohms Law, Thevenin
  Laws etc
• - Identify the parameters given
• - Analyze into the input/output for the system
  and build a loop using electric circuits law.

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Design Operations

• If the transistor and supplies are specified, the
  design process will simply determine the required
  resistor for a particular design.
• Once the theoretical values of the resistors are
  determined, the nearest standard commercial
  values are normally chosen and any variations due
  to not using the exact resistance values are
  accepted as part of the design.
• RunknownVR/IR

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Design of a bias circuit with an emitter feedback
resistor
The emitter resistor is ¼ to 1/10 of the supply
voltage
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Design of a bias circuit with an emitter feedback
resistor

• RE and RC cannot proceed directly from the
  information just specified.
• RE to provide dc bias stabilization so that the
  change of collector current due to leakage
  currents in the transistor and the transistor
  beta would not cause a large shift in the
  operating point.
• The RE cannot be unreasonably large because the
  voltage across it limits the range of swing of
  the voltage from collector to emitter.
• VE typically ¼ -1/10 from supply voltage

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Example 3

• Determine the resistor values for the network,
  for
• the indicated operating point and supply voltage.

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Design of a current-gain-stabilized circuit (beta
independent)
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Transistor as switching networks

• Transistor works as an inverter in computer
  circuits.
• Operating point switch from cut-off to
  saturation along the
• load line for proper inversion.
• In order to understand, we assume that
• ICICEO0mA
• VCEVsat0V
• One must understand the transistor graph output
  and
• load-line analysis to describe and discuss
  about the
• transistor switching networks.

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Transistor as switching networks
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Time interval
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Time interval (continued)
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Troubleshooting

• How to define and encounter transistor circuit
  problem?

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