8086 Interrupts and Interrupt Applications

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Chapter 8

• 8086 Interrupts and Interrupt Applications

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Interrupts

• An interrupt is a break in the flow of execution
  of program
• the CPU is interrupted
• When an interrupt occurs, the CPU deals with the
  interruption, then carries on where it left off

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Types of Interrupts

• Hardware
• an external signal is applied to the NMI input
  pin or the INTR input pin
• NMI - non-maskable interrupt
• INTR - interrupt
• used to deal with I/O devices needing attention
• Software
• execution of the interrupt instructionINT
• some error condition is produced by the execution
  of an instruction
• such as divide by zero

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Interrupt Handling

• When an interrupt is requested
• the CPU finishes executing current instruction
• pushes flag register onto stack
• disables the INTR input by clearing the IF
  (interrupt flag) in the flag register
• clears the TF (trap flag) in the flag register
• pushes the current CS contents onto the stack
• pushes the current IP contents onto the stack
• does an indirect far jump to the start of the ISR
  (Interrupt Service Routine)
• Hardware and software interrupts are handled the
  same

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Interrupt Handling (cont.)

• Executes ISR like a normal procedure, EXCEPT
• ISRs use an IRET instruction rather than RET
• this pops IP, CS, and the Flag registers
• ISRs can be interrupted!

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Setting up an Interrupt-Pointer Table

• The first 1 KB of memory is set aside as a table
  for storing the starting addresses of ISR
• these are address 00000H to 003FFH
• you need 4 bytes to store the CS and IP values
  for each ISR
• thus the table can hold the addresses for 256
  ISRs
• Terms
• Interrupt vector/pointer - the starting address
  of an ISR
• Interrupt vector/pointer table - the table
  containing the starting addresses of the ISRs

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Classifying Interrupts

• An ISR is identified by a number from 0 to 255
• this called its type
• An interrupt pointer/vector is a doubleword
• the low word contains the IP value
• the high word contains the CS value

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Dedicated Interrupts

• Type 0 to Type 4 interrupts are dedicated to
  specific interrupts
• Type 5 to Type 31 interrupts are reserved by
  Intel for more complex microprocessors
• Type 32 to Type 255 interrupts can be user
  specified for dealing with hardware or software
  interrupts

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Type 0 Interrupt Example

• Type 0 specifies a divide by zero interrupt
• Recall DIV instruction
• whenever a quotient from DIV or IDIV operation is
  too large to fit in the result register, a type 0
  interrupt happens automatically
• Its up to the programmer to handle this
  interrupt
• one possible is to set a programmer-defined error
  flagBAD_DIV_FLAG

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Initialization List

• Initialize the interrupt-vector table
• use the ES register
• the starting address of our type 0 ISR needs to
  be in locations 00000H and 00002H
• Set up the data segment
• include a declaration for the BAD_DIV_FLAG
• Initialize DS
• Set up a stack
• Initialize SS and SP

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Single-Step Interrupt - Type 1

• If the TF (trap flag) is set, a type 1 interrupt
  will automatically occur
• To implement single-stepping, such as in a
  debugger
• set the trap flag
• write an ISR that saves all registers on the
  stack, so they can be examined
• load the address of the ISR into the addresses
  00004H and 00006H

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Nonmaskable Interrupt - Type 2

• Type 2 interrupt automatically occurs when the
  CPU receives a low-to-high transition on its NMI
  pin
• this type of interrupt cannot be masked by any
  program instructions
• normally used to signal that some external
  system/device must be taken care of
• pressure sensor on a large steam boiler
• save data in case of a power failure

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Breakpoint Interrupt -Type 3

• This type of interrupt is produced by executing
  an INT 3 instruction
• no automatic triggers
• Useful for debugging
• many debuggers implement breakpoints by inserting
  an INT 3 instruction before the specified
  instruction
• the Type 3 ISR may then store all the registers
  so that they can be examined by the user

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Overflow Interrupt - Type 4

• This type of interrupt may be produced if the OF
  (Overflow flag) is set but not automatically
  triggered
• OF will be set if the signed result of an
  arithmetic operation on 2 signed numbers is too
  large to be represented in the destination
• 01101100 (108 decimal) 01010001 (81 decimal),
  remember that these are signed!

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Overflow Interrupt (cont.)

• Can handle OF error using a JO instruction
  following arithmetic operation
• Can also use the INTO instruction
• this specifies to Interrupt on Overflow
• if OF is set (1), will execute ISR contained in
  the type 4 addresses in the vector table
• INTO is advantageous because you can use the same
  ISR for many programs

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Software Interrupts

• How do I test out my ISR that handles a type 2
  interrupt without directly signaling the NMI pin?
• Use a software interrupt
• INT 2 test out NMI ISR
• You can specify values 0 - 255 (decimal) as
  operands to the INT instruction

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INTR Interrupts

• These are hardware interrupts
• can be disabled by clearing IF
• CLI disable interrupts
• can be enabled by setting IF
• STI enable interrupts
• The interrupt type is sent to the 8086 from an
  external hardware device
• could be an 8259A priority interrupt controller
• Remember, IF is automatically cleared in response
  to any type of 8086 interrupt

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Why Disable INTR Interrupts?

• Reason 1
• To prevent an INTR interrupt from interrupting a
  higher priority interrupt
• Interrupt priorities
• Highest - Divide Error, INT n, INTO
• Lower - NMI
• Still Lower - INTR
• Lowest - Single-Step

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• Reason 2
• To prevent an interrupt from continuously
  interrupting itself
• The INTR input is active highwhenever INTR input
  is high and IF is set, the 8086 will be
  interrupted
• After IRET, flag is popped
• INTR could still possibly be receiving the same
  high signal and cause another interrupt
• it is the responsibility of the external hardware
  sending the INTR signal to avoid this problem

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A Priority Interrupt Controller

• Interrupt signal is actually sent to the
  interrupt controller on one of its input lines
• Controller then signals 8086 INTR input
• 8086 will only respond is IF is set
• 8086 Response
• Sends 2 INTA (interrupt acknowledge) signals to
  controller
• first one tells controller to get ready to send
  interrupt
• second one tells controller to send it
• Controller sends in the interrupt type on the
  data bus to be read by the 8086

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Why use an external controller?

• Can serve as a funnel of interrupts to the CPU
• Can also serve as an arbitrator in the case when
  multiple interrupts arrive at the same time

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More on Priorities

• Scenario 1
• IF is set and an INTR signal is received during
  the execution of a divide that produces a type 0
  interrupt
• what happens?
• Scenario 2
• NMI input is signaled during the execution of a
  divide that produces a type 0 interrupt
• what happens? Is this what you wouldve expected?

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Interrupt-driven data input

• this is an alternative to polling
• the CPU continuously reads and tests some input
  waiting to see if theres any data
• Are we there yet? Are we there yet? Are we
  there yet?
• this can be less than efficient because the CPU
  is busy polling, rather than doing useful work
• the CPU is able to do useful tasks until it is
  interrupted with input data
• an external device sends an interrupt (INTR or
  NMI) signal, and the ISR handles manipulating
  this data
• Were there!
• the I/O operation now only occupies a small
  percentage of CPU time

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Other Hardware Interrupt Applications

• Counting applications
• can be used to count finished goods off an
  assembly line
• Timing applications
• this is an alternative to the WAIT_1MS procedure
  we wrote in chapter 4
• wasnt that wasteful
• Real-time clocks

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8254 Software-Programmable Timer/Counter

• This is a specific timer/counter device that can
  be programmed for a specific application
• An example
• connect the 8254 to the 8259 interrupt vector,
  which is connected to an SDK-86