ELEN 468 Advanced Logic Design

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ELEN 468Advanced Logic Design

• Lecture 5
• User-Defined Primitives

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Primitives

• Pre-defined primitives
• Total 26 pre-defined primitives
• All combinational
• Tri-state primitives have multiple output, others
  have single output
• User-Defined Primitives (UDP)
• Combinational or sequential
• Single output
• UDP vs. modules
• Used to model cell library
• Require less memory
• Simulate faster

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UDP Combinational Behavior

• primitive mux_prim ( out, select, a, b )
• output out
• input select, a, b
• table
• // select a b out
• 0 0 0 0 // Each column -gt a port
• 0 0 1 0 // Last column -gt single output
• 0 0 x 0 // Input port column order
  port list order
• 0 1 0 1 // No inout port
• 0 1 1 1 // Only 0, 1, x on input and
  output
• 0 1 x 1 // A z input is treated as
  x
• 1 0 0 0 // If an input vector is not in
  table, output -gt x
• 1 1 0 0
• 1 x 0 0
• 1 0 1 1
• 1 1 1 1
• 1 x 1 1
• x 0 0 0 // Reduce pessimism
• x 1 1 1 // Without these 2 rows, output
  x for select x

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Shorthand Notation

• primitive mux_prim ( out, select, a, b )
• output out
• input select, a, b
• table
• //select a b out
• 0 0 ? 0 // ? gt iteration of table
  entry over 0, 1, x.
• 0 1 ? 1 // i.e., dont care on the
  input
• 1 ? 0 0
• 1 ? 1 1
• ? 0 0 0
• ? 1 1 1
• endtable
• endprimitive

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UDP Sequential Behavior

• In table description, n2 columns for n input
• n input columns internal state column output
  (next state) column
• Output port -gt reg variable

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Level-sensitive Behavior

• primitive transparent_latch(out, enable, in)
• output out
• input enable, in
• reg out
• table
• //enable in state out/next_state
• 1 1 ? 1
• 1 0 ? 0
• 0 ? ? - // - -gt no change
• x 0 0 -
• x 1 1 -
• endtable
• endprimitive

enable
Transparent latch
in
out
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Edge-sensitive Behavior

• primitive d_flop( q, clock, d )
• output q
• input clock, d
• reg q
• table
• // clock d state q/next_state
• (01) 0 ? 0 // Parentheses indicate
  signal transition
• (01) 1 ? 1 // Rising clock edge
• (0?) 1 1 1
• (0?) 0 0 0
• (?0) ? ? - // Falling clock edge
• ? (??) ? - // Steady clock
• endtable
• endprimitive

clock
d
q
d_flop
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Mixed Behavior

• primitive jk_prim(q, clk, j, k, preset, clr)
• output q
• input clk, j, k, preset, clr
• reg q
• table
• // clk j k pre clr state
  q/next_state
• ? ? ? 0 1 ? 1
• ? ? ? 1 1 1 // -gt
  (??)
• ? ? ? 1 0 ? 0
• ? ? ? 1 0 0
• r 0 0 1 1 ? - // r -gt
  (01)
• r 0 1 1 1 ? 0
• r 1 0 1 1 ? 1
• b ? ? ? ? - // b -gt
  iterate through 0 and 1
• endtable
• endprimitive

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Additional UDP Notations
Symbol Interpretation
? Iteration of 0, 1, x
b Iteration of 0, 1
- No change
(vw) Transition from v to w
All transition input (??)
r Transition (01)
f Transition (10)
p Iteration of (01), (0x), (x1)
n Iteration of (10), (x0), (1x)
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Initialization of Sequential Primitives

• primitive d_flop( q, clock, data )
• output q
• input clock, data
• reg q
• initial q 0 // Set initial value of q
• table
• endtable
• endprimitive

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Exercises
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True or False

• A Verilog reg variable can be the output of a
  pre-defined primitive, false
• A Verilog net variable cannot be assigned value
  by continuous assignment, false
• All module ports are scalars, false

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Find Syntax Error

• reg 70 a, 150 b
• reg 70 a
• reg 150 b
• integer 70 count_index
• integer count_index70

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Problems

• If a0010, b1010, c0001, what is
  a,b3,b1,c2,c0 ? 00101101
• A 0101, B 1001, what is
• A B ? 0
• A (B) ? 0101 0 0
• In UDP notations, what is the difference between
  r and p?