ELEN 468 Advanced Logic Design

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ELEN 468Advanced Logic Design

• Lecture 30
• VLSI Transistor/Gate Characteristics

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MOS Transistor Technology
gate
gate
drain
source
source
n
n
p
p
n well
p substrate
s
d
g
g
s
d
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I-V Characteristics

• Cutoff region
• Vgs lt Vt
• Ids 0
• Linear region
• Vgs gt Vt, 0 lt Vds lt Vgs-Vt
• Ids B(Vgs-Vt)Vds V2ds/2
• Saturation region
• Vgs gt Vt, 0 lt Vgs-Vt lt Vds
• Ids B(Vgs-Vt)2/2
• B a W/L

d
g
s
Ids
Vds
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Switching Characteristics
Vin
Vdd
in
out
d
t
Vout
Ids
t
Vds
tfall
tdelay
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Falling and Rising Procedure
Input rising
Input falling
Vdd
Vdd
Vdd
Vdd
out
out
out
out
Saturation
Linear
Saturation
Linear
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Falling Time

• Falling time t1 t2
• t1 Vout drops from 0.9Vdd to Vdd-Vt
• t2 Vout drops from Vdd-Vt to 0.1Vdd
• Falling time rising time k
  C / (B Vdd)
• Delay Falling time / 2

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Cascaded Drivers
k
1
2
3
CL

• p stage ratio
• size( i1 ) p ? size( i )
• R( i1 ) R( i ) / p
• C( i1 ) p ? C( i )

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Delay of Cascaded Drivers

• Delay between stage i and i1
• R( i ) ? C( i1 ) p ? R( i ) ? C( i )
• Total delay from stage 1 to stage k
• p?R(1)?C(1) p?R(2)?C(2)
  p?R(k-1)?C(k-1) R(k)?CL
  p?R(1)?C(1) p?R(1)?C(1)
  p?R(1)?C(1) R(1)?CL / pk-1
  (k-1)?p?R(1)?C(1) R(1)?CL / pk-1

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Minimum Delay Stage Ratio

• A (k-1)?R(1)?C(1), B R(1)?CL
• t A?p B?p1-k
• Let derivative t 0
• A (1-k)?B?p-k 0
• pk (k-1) ?B/A CL / C(1)
• p CL / C(1)1/k

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Optimal Number of Stages

• CL C(1) pk
• k ln(CL/C(1)) / ln p
• t k?p?R(1)?C(1)
  (ln (CL/C(1)) / ln p
  1)?p?R(1)?C(1)
• Delay t reaches minimum when p 2.72

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Gate Power Dissipation

• Leakage power
• Dynamic power
• Short circuit power

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Leakage Power

• Static
• Leakage current a ? Vdd
• Leakage current b/Vt
• Killer to CMOS technology

Vdd
Vdd
Leakage
out
out
Leakage
Linear
Saturation
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Dynamic Power

• Occurs at each switching
• Pd CL?Vdd2?fp
• fp switching frequency

Vdd
Vdd
out
out
Linear
Saturation
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Short Circuit Power

• During switching, there is a short moment when
  both PMOS and CMOS are partially on
• Ps Q?(Vdd-Vt)3?tr?fp
• tr rising time

Input falling
Vdd
Vdd
out
out
Input rising