ELEN 468 Advanced Logic Design

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ELEN 468Advanced Logic Design

• Lecture 4
• Data Types and Operators

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Variables

• Represent values of signals in physical circuit
  in a digital format
• Nets
• Represent physical connectivity
• Registers
• Abstractions of storage elements
• Nets and registers may be either scalars or
  vectors

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Storage Variable

• Storage variable register
• reg, integer, real, realtime, time
• Abstraction of storage element
• Need not correspond directly to physical storage
  element in circuit
• Static its value is assigned under program
  flow

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Value Assignment

• Explicitly through behavioral statements
• Implicitly driven by a gate
• A net may be assigned value explicitly only
  through continuous assignment
• A register variable may be assigned value only
  within a behavior

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Verilog Nets

• wire (default)
• tri
• wand
• wor
• triand
• trior

tri
triand/trior
wand/wor
Not recommended!
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Example
ctrl

• tri y
• bufif1(y, x, ctrl)
• triand y
• bufif1(y, x1, ctrl1)
• bufif1(y, x2, ctrl2)

y
x
Three-state gate, page 651
ctrl1
x1
ctrl2
y
x2
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Truth Tables
wire/tri 0 1 x z 0 0 x x 0 1 x 1 x 1
x x x x x z 0 1 x z
triand / wand 0 1 x z 0 0 0 0 0
1 0 1 x 1 x 0 x x x z 0 1 x z
trior/wor 0 1 x z 0 0 1 x 0 1
1 1 1 1 x x 1 x x z 0 1 x z
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More Verilog Nets
Vdd
tri0

• supply0
• supply1
• tri0
• tri1
• trireg

Vdd
supply1
supply0
Gnd
Gnd
tri1
a
b
when a b 0, the line maintains its value
trireg
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Net Declaration

• wire70 data_bus // 8-bit vector wire,
  data_bus7 -gt MSB
• wire03 control_bus // control_bus0 -gt MSB
• data_bus5, data_bus35, data_busk2 //
  access
• wire scalared70 bus_a // scalared is
  default
• wire vectored70 bus_b // Individual bits
  may not be referenced
• wire y1, z_5 // Multiple declaration
• wire A BC, D EF // Implicit continuous
  assignment
• wand A, B, C
• trireg70 A

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Initial Values

• At time tsim 0
• Nets driven by primitives, module or continuous
  assignment is determined by their drivers,
  default value x
• Net without driver, its initial value z
• Default initial value for register -gt x

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Register Data Types

• reg stores a logic value
• integer support computation
• time stores time as a 64-bit unsigned quantity
• real stores values as real numbers
• realtime store time values as real numbers

• Assigned value only within a procedural
  statement, a user defined sequential primitive,
  task or function
• A reg object may never be output of
• a primitive gate
• the target of a continuous assignment
• Undeclared identifier is assumed as a net, which
  is illegal within behavior

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Addressing Net and Register Variables

• MSB of a part-select of a register leftmost
  array index
• LSB rightmost array index
• If index of part-select is out of bounds, x is
  returned
• If word 70 8b00000100
• word 30 4
• word 51 2
• Integer array
• integer A30

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Variables and Ports
Variable type Input port Output port Inout port
Net Yes Yes Yes
Register No Yes No
An input port is implicitly a net variable
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Memories
Memory size
Word size

• reg310 cache_memory01023
• reg310 word_register
• reg70 instr_register
• word_register cache_memory17
• // a loop
• instr_registerk word_registerk4

• Individual bits within a memory cannot be
  addressed directly
• The word is fetched to a register, then bit can
  be accessed

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Scope of a Variable

• The scope of a variable is the module, task,
  function, or named procedural block (begin end)
  in which it is declared

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De-Reference

• To reference a variable defined inside an
  instantiated module
• X.w
• X.Y.Z.w

Module A - Instance X
wire w
Module B - Instance Y
Module C - Instance Z
wire w
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Example of De-referencing
module testbench() reg 30 a, b wire
30 y adder M1 (y, a, b) initial
monitor(time,,, M1.c) endmodule module
adder(y, a, b) wire c endmodule
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Strings

• Verilog does not have type for strings
• A string must be stored in a register array

reg 8num_char-1 0 string_holder
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Constants

• Declared with keyword parameter
• Value may not be changed during simulation

parameter width 32, depth 1024 parameter
real_value 6.22 parameter av_delay (dmin
dmax)/2
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Direct Substitution of Parameters

• module modXnor(y, a, b)
• parameter size8, delay15
• output size-10 y
• input size-10 a, b
• wire size-10 delay y ab
• endmodule
• module param
• wire 70 y1
• wire 30 y2
• reg 70 b1, c1
• reg 30 b2, c2
• modXnor G1(y1, b1, c1)
• modXnor (4,5) G2(y2, b2, c2)
• endmodule

• Value of a constant can be changed during
  compilation
• Dont confuse with assigning delay to primitives
• Module instantiation do not have delay
• Primitives do not have parameters

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Indirect Substitution of Parameters

• module param
• wire 70 y1
• wire 30 y2
• reg 70 b1, c1
• reg 30 b2, c2
• modXnor G1(y1, b1, c1)
• modXnor G2(y2, b2, c2)
• endmodule
• module annotate
• defparam
• param.G2.size 4
• parem.G2.delay 5
• endmodule

• Declare a separate module where defparam is used
  with hierarchical pathname

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Operators
Operator Number of Operands Result
Arithmetic 2 Binary word
Bitwise 2 Binary word
Reduction 1 Bit
Logical 2 Boolean value
Relational 2 Boolean value
Shift 1 Binary word
Conditional 3 Expression
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Arithmetic Operators

• 2s complement representation
• MSB is sign bit
• For scalar and vector
• For nets and registers

Symbol Operator
Addition
- Subtraction
Multiplication
/ Division
Modulus
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Bitwise Operators

• (101011) 010100
• (010101) (001100) 000100
• (010101) (001100) 011001

Symbol Operator
Bitwise negation
Bitwise and
Bitwise inclusive or
Bitwise exclusive or
, Bitwise exclusive nor
Shorter word will extend to the size of longer
word by padding bits with 0
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Reduction Operators
Symbol Operator
Reduction and
Reduction nand
Reduction or
Reduction nor
Reduction xor
, Reduction xnor
(101011) 0 (001100) 1

• Unary operators
• Return single-bit value

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Logical Operators

• Case equality operators detect exact bit-by-bit
  match, including x or z
• The logical equality operator is less
  restrictive, x is returned for any ambiguity
• Verilog is loosely typed - OK to use AB when A
  and B are vectors
• AB returns true if both words are non-zero
  integers
• can recognize x and z while would
  return x for ambiguity

Symbol Operator
! Logical negation
Logical and
Logical or
Logical equality
! Logical inequality
Case equality
! Case inequality
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Relational and Shift Operators
Relational operators Shift operators
lt ltlt
lt gtgt
gt
gt

• if ( ( a lt b ) ( a gt c ) )
• result a ltlt 3

• Relational operators return x for ambiguity
• 0xxx gt 1xxx returns 1

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Conditional Operator

• Y ( A B ) ? C D
• wire 10 select
• wire 150 D1, D2, D3, D4
• wire 150 bus (select 2b00) ? D1
• (select 2b01) ? D2
• (select 2b10) ? D3
• (select 2b11) ? D4 16bx

? 0 1 X
0 0 X X
1 X 1 X
X X X X

• z is not allowed in conditional_expression
• If conditional_expression is ambiguous, both
  true_expression and false_expression are
  evaluated bitwisely according to the truth table
  to get the result

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Operands

• A Verilog operand may be compose of
• Nets
• Registers
• Constants
• Numbers
• Bit-select of a net or a register
• Part-select of a net or a register
• A function call
• Concatenation of any of above

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Operator Precedence
Operator precedence Operator symbol
Highest - ! (unary)
/
- (binary)
ltlt gtgt
lt lt gt gt
! !





Lowest ?
Parentheses for precaution !