CDA 5155

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CDA 5155

• Out-of-order execution
• Scoreboarding and Tomasulo
• Week 2

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A more realistic pipeline
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Dependencies

• Read after Write (RAW) true dependency
• add 1 2 3 nand 3 4 5
• Write after Read (WAR) Anti-dependency
• add 1 2 3 nand 5 6 2
• Write after Write (WAW) output dependency
• add 1 2 3 nand 5 6 3
• Read after Read (RAR) usually not a problem
• add 1 2 3 nand 1 5 6

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Out-of-order execution

• Variable latencies make out-of-order execution
  desirable
• How do we prevent WAR and WAW hazards?
• How do we deal with variable latency?
• Forwarding for RAW hazards harder.

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CDC 6600
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Scoreboard a bookkeeping technique

• Out-of-order execution divides ID stage
• 1. Issuedecode instructions, check for
  structural hazards
• 2. Read operandswait until no data hazards, then
  read operands
• Scoreboards date to CDC6600 in 1963
• Instructions execute whenever not dependent on
  previous instructions and no hazards.
• CDC 6600 In order issue, out-of-order execution,
  out-of-order commit (or completion)
• No forwarding!
• Imprecise interrupt/exception model

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Scoreboard Architecture(CDC 6600)
Functional Units
Registers
SCOREBOARD
Memory
Fetch/Issue
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Scoreboard Implications

• Out-of-order completion gt WAR, WAW hazards?
• Solutions for WAR
• Stall writeback until all prior uses of the
  destination register have been read
• Read registers only during Read Operands stage
• Solution for WAW
• Detect hazard and stall issue of new instruction
  until other instruction completes
• Need to have multiple instructions in execution
  phase gt multiple execution units or pipelined
  execution units
• Scoreboard keeps track of dependencies between
  instructions that have already issued.
• Scoreboard replaces ID, EX, M and WB with 4 stages

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Four Stages of Scoreboard Control

• Issuedecode instructions check for structural
  hazards (ID1)
• Instructions issued in program order (for hazard
  checking)
• Dont issue if structural hazard
• Dont issue if instruction is output dependent on
  any previously issued but uncompleted instruction
  (no WAW hazards)
• Read operandswait until no data hazards, then
  read operands (ID2)
• All real dependencies (RAW hazards) resolved in
  this stage, since we wait for instructions to
  write back data.
• No forwarding of data in this model!

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Four Stages of Scoreboard Control

• Executionoperate on operands (EX)
• The functional unit begins execution upon
  receiving operands. When the result is ready, it
  notifies the scoreboard that it has completed
  execution. This includes memory ops.
• Write resultfinish execution (WB)
• Stall until no WAR hazards with previous
  instructionsExample DIV 1 2 3 ADD 3 4 5
  NAND 6 7 4CDC 6600 scoreboard would stall
  NAND until ADD reads operands

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Three Parts of the Scoreboard

• Instruction status Which state the instruction
  is in
• Functional unit statusIndicates the state of
  the functional unit (FU). 9 fields for each
  functional unit
• Busy Indicates whether the pipeline unit is busy
  or not
• Op Operation to perform in the unit (e.g., or
  )
• Fi Destination register (for writeback and WAW
  check)
• Fj,Fk Source-register numbers (for reg read and
  WAR check)
• Qj,Qk Functional units producing source
  registers Fj, Fk (wake up)
• Rj,Rk Flags indicating when Fj, Fk are ready
  (and when already read)
• Register result statusIndicates which
  functional unit will write each register, if one
  exists. Blank when no pending instructions will
  write that register

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Scoreboard Example
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Detailed Scoreboard Pipeline Control
Pipeline available and no WAW possible
Both src operands are available
no WAR hazard (no earlier instr has yet to read
the dest reg to be written)
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Scoreboard Example Cycle 1
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Scoreboard Example Cycle 2

• Issue 2nd LD? No Integer pipeline is busy.

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Scoreboard Example Cycle 3

• Issue MULT? No, still trying to issue LD

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Scoreboard Example Cycle 4
0
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Scoreboard Example Cycle 5
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Scoreboard Example Cycle 6

• Issue MULT? Yes, but cant read F2 until LD
  completes.

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Scoreboard Example Cycle 7

• Read multiply operands? No, F2 is not ready

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Scoreboard Example Cycle 8a(First half of clock
cycle)

• LD completes. Update Multd and subd waiting on F2

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Scoreboard Example Cycle 8b(Second half of
clock cycle)
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Scoreboard Example Cycle 9
Note Remaining

• Read operands for MULT SUB? yes
• Issue ADDD? No, add pipline busy

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Scoreboard Example Cycle 10
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Scoreboard Example Cycle 11
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Scoreboard Example Cycle 12

• Read operands for DIVD? No, F0 is not available

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Scoreboard Example Cycle 13
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Scoreboard Example Cycle 14
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Scoreboard Example Cycle 15
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Scoreboard Example Cycle 16
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Scoreboard Example Cycle 17

• Why not write result of ADD???

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Scoreboard Example Cycle 18
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Scoreboard Example Cycle 19
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Scoreboard Example Cycle 20
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Scoreboard Example Cycle 21
no no

• WAR Hazard is now gone... Complete the add

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Scoreboard Example Cycle 22
37

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Scoreboard Example Cycle 61
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Scoreboard Example Cycle 62
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Scoreboard Example Cycle 62

• In-order issue out-of-order execute commit

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CDC 6600 Scoreboard

• Historical context
• Speedup 1.7 from compiler 2.5 by hand BUT slow
  memory (no cache) limits benefit
• Limitations of 6600 scoreboard
• No forwarding hardware
• Limited to instructions in basic block (small
  window)
• Small number of functional units (structural
  hazards), especially integer/load store
  units
• Do not issue on structural hazards
• Wait for WAR hazards
• Prevent WAW hazards
• Precise interrupts?

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IBM 360/91
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Another Dynamic Algorithm Tomasulos Algorithm

• For IBM 360/91 about 3 years after CDC 6600
  (1966)
• Goal High Performance without special compilers
• Differences between IBM 360 CDC 6600 ISA
• IBM has only 2 register specifiers/instr vs. 3 in
  CDC 6600
• IBM has 4 FP registers vs. 8 in CDC 6600
• IBM has memory-register ops
• Small number of floating point registers
  prevented interesting compiler scheduling of
  operations
• This led Tomasulo to try to figure out how to get
  more effective registers renaming in hardware!
• Why Study? The descendants of this have
  flourished!
• Alpha 21264, HP 8000, MIPS 10000, Pentium II,
  PowerPC 604,

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Tomasulo Algorithm vs. Scoreboard

• Control buffers distributed with Function Units
  (FU) vs. centralized in scoreboard
• FU buffers called reservation stations have
  pending operands
• Registers in instructions replaced by values or
  pointers to reservation stations(RS) called
  register renaming
• avoids WAR, WAW hazards
• More reservation stations than registers, so can
  do optimizations compilers cant
• Results to FU from RS, not through registers,
  over Common Data Bus that broadcasts results to
  all FUs
• Load and Stores treated as FUs with RSs as well
• Integer instructions can go past branches,
  allowing FP ops beyond basic block in FP queue

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Tomasulo Organization
FP Registers
From Mem
FP Op Queue
Load Buffers
Load1 Load2 Load3 Load4 Load5 Load6
Store Buffers
Add1 Add2 Add3
Mult1 Mult2
Reservation Stations
To Mem
FP adders
FP multipliers
Common Data Bus (CDB)
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Reservation Station Components

• Op Operation to perform in the unit (e.g., or
  )
• Vj, Vk Value of Source operands
• Store buffers has V field, result to be stored
• Qj, Qk Reservation stations producing source
  registers (value to be written)
• Note No ready flags as in Scoreboard Qj,Qk0 gt
  ready
• Store buffers only have Qi for RS producing
  result
• Busy Indicates reservation station or FU is
  busy
• Register result statusIndicates which
  functional unit will write each register, if one
  exists. Blank when no pending instructions that
  will write that register.

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Three Stages of Tomasulo Algorithm

• 1. Issueget instruction from FP Op Queue
• If reservation station free (no structural
  hazard), control issues instr sends operands
  (renames registers).
• 2. Executeoperate on operands (EX)
• When both operands ready then execute if not
  ready, watch Common Data Bus for result
• 3. Write resultfinish execution (WB)
• Write on Common Data Bus to all awaiting units
  mark reservation station available
• Normal data bus data destination (go to bus)
• Common data bus data source (come from bus)
• 64 bits of data 4 bits of Functional Unit
  source address
• Write if matches expected Functional Unit
  (produces result)
• Does the broadcast

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Tomasulo Example
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Tomasulo Example Cycle 1
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Tomasulo Example Cycle 2
Note Unlike 6600, can have multiple loads
outstanding (This was not an inherent limitation
of scoreboarding)
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Tomasulo Example Cycle 3

• Note registers names are removed (renamed) in
  Reservation Stations MULT issued vs. scoreboard
• Load1 completing what is waiting for Load1?

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Tomasulo Example Cycle 4

• Load2 completing what is waiting for Load1?

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Tomasulo Example Cycle 5
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Tomasulo Example Cycle 6

• Issue ADDD here vs. scoreboard?

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Tomasulo Example Cycle 7

• Add1 completing what is waiting for it?

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Tomasulo Example Cycle 8
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Tomasulo Example Cycle 9
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Tomasulo Example Cycle 10

• Add2 completing what is waiting for it?

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Tomasulo Example Cycle 11

• Write result of ADDD here vs. scoreboard?
• All quick instructions complete in this cycle!

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Tomasulo Example Cycle 12
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Tomasulo Example Cycle 13
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Tomasulo Example Cycle 14
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Tomasulo Example Cycle 15
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Tomasulo Example Cycle 16
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Faster than light computation(skip a couple of
cycles)
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Tomasulo Example Cycle 55
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Tomasulo Example Cycle 56

• Mult2 is completing what is waiting for it?

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Tomasulo Example Cycle 57

• Once again In-order issue, out-of-order
  execution and completion.

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Compare to Scoreboard Cycle 62

• Why take longer on scoreboard/6600?
• Structural Hazards
• Lack of forwarding

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Tomasulo v. Scoreboard(IBM 360/91 v. CDC 6600)

• Pipelined Functional Units Multiple Functional
  Units
• (6 load, 3 store, 3, 2x/) (1 load/store, 1,
  2x, 1)
• window size 14 instructions 5 instructions
  
• No issue on structural hazard same
• WAR renaming avoids stall completion
• WAW renaming avoids stall issue
• Broadcast results from FU Write/read registers
• Control reservation stations central
  scoreboard

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Tomasulo Drawbacks

• Complexity
• delays of 360/91, MIPS 10000, IBM 620?
• Many associative stores (CDB) at high speed
• Performance limited by Common Data Bus
• Each CDB must go to multiple functional units
  ?high capacitance, high wiring density
• Number of functional units that can complete per
  cycle limited to one!
• Multiple CDBs ? more FU logic for parallel assoc
  stores
• Non-precise interrupts!
• We will address this later

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Tomasulo Loop Example

• Loop LD F0 0 R1
• MULTD F4 F0 F2
• SD F4 0 R1
• SUBI R1 R1 8
• BNEZ R1 Loop
• Assume Multiply takes 4 clocks
• Assume first load takes 8 clocks (cache miss),
  second load takes 1 clock (hit)
• To be clear, will show clocks for SUBI, BNEZ
• Reality integer instructions ahead

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Loop Example
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Loop Example Cycle 1
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Loop Example Cycle 2
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Loop Example Cycle 3

• Implicit renaming sets up DataFlow graph

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Loop Example Cycle 4

• Dispatching SUBI Instruction

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Loop Example Cycle 5

• And, BNEZ instruction

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Loop Example Cycle 6

• Notice that F0 never sees Load from location 80

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Loop Example Cycle 7

• Register file completely detached from
  computation
• First and Second iteration completely overlapped

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Loop Example Cycle 8
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Loop Example Cycle 9

• Load1 completing who is waiting?
• Note Dispatching SUBI

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Loop Example Cycle 10

• Load2 completing who is waiting?
• Note Dispatching BNEZ

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Loop Example Cycle 11

• Next load in sequence

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Loop Example Cycle 12

• Why not issue third multiply?

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Loop Example Cycle 13
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Loop Example Cycle 14

• Mult1 completing. Who is waiting?

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Loop Example Cycle 15

• Mult2 completing. Who is waiting?

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Loop Example Cycle 16
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Loop Example Cycle 17
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Loop Example Cycle 18
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Loop Example Cycle 19
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Loop Example Cycle 20
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Why can Tomasulo overlap iterations of loops?

• Register renaming
• Multiple iterations use different physical
  destinations for registers (dynamic loop
  unrolling).
• Reservation stations
• Permit instruction issue to advance past integer
  control flow operations
• Also buffer old values of registers - totally
  avoiding the WAR stall that we saw in the
  scoreboard.
• Other idea Tomasulo building DataFlow graph on
  the fly.

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Summary 1

• Reservations stations implicit register renaming
  to larger set of registers buffering source
  operands
• Prevents registers as bottleneck
• Avoids WAR, WAW hazards of Scoreboard
• Allows loop unrolling in HW
• Not limited to basic blocks (integer units gets
  ahead, beyond branches)
• Helps cache misses as well
• Lasting Contributions
• Dynamic scheduling
• Register renaming
• Load/store disambiguation (see fig 3.5 execute
  stage)
• 360/91 descendants are Pentium II PowerPC 604
  MIPS R10000 HP-PA 8000 Alpha 21264