Review of Vertex Detector R

1
Review of Vertex Detector RD for International
Linear Collider
ILC Vertex Detector RD - CCD (ISSI) -
MAPS - DEPFET Summary
Jik Lee Seoul National Univ.
2
International Linear Collider

• electron and positron linear collider
• at energy from 500 GeV up to 1 TeV
• and electron beam polarization gt 80
• and upgrade option for positron polarization
• ? Accelerator technology chosen cold
• 3 Projects at
• - DESY (TeV Energy Superconducting Linear
  Accelerator)
• - Japan (Global Linear Collider)
• - US (Next Linear Collider)

3
? ILC Detectors
Main Tracker drives ILC detector configurations
Gaseous Tracker
HUGE
Silicon Tracker
Large/Huge
Medium/Large
3 tesla
4 tesla
5 tesla
4
ILC Environment for Vertex Detector
SVD in SD design
Silicon based vertex detector(s) CCD, MAPS,
DEPFET, and more - 4-5 cylindrical layers
able to do stand alone tracking -
background tolerance - fast (due to problem of
overlapping events)
Beam Structures
Warm Cold
bunch/train 192 2820
train length 269 ns 950 µs
bunch spacing 1.4 ns 337 ns
train/s 150/120 Hz 5 Hz
gap/train 6.6 ms 199 ms
5
ILC Vertex Detector Requirements

• Close to IP ? reduce extrapolation error
• Pixel Size20x20mm2 ? sPoint 3 mm 800M
  channels
• Layer Thickness lt0.1X0
• suppression of g conversions
• minimize multiple scattering
• LC environment requires vertex sensors which are
  substantially thinner and
• more precise than LHC and thus motivates new
  directions for RD on
• vertex sensors
• 1/5 rbp, 1/30 pixel size, 1/3 thinner
  than LHC sensors

6
Vertex Detector RD Groups
CCD LCFI (Bristol, Glasgow, Lancaster,
Liverpool, Oxford, RAL) UK Niigata, KEK,
Tohoku, Toyama Japan Oregon, Yale, SLAC
US MAPS Strasbourg (IReS, LEPSI)
DAPNIADESY
France
RussiaGermany Brunel, Birmingham, CCLRC,
Glasgow, Liverpool, RAL UK DEPFET Bonn,MPI
Germany
7
Vertex Detector Comparison
Do not take this seriously. It could be wrong due
to my personal bias and ignorance!
CCD MAPS DEPFET
Resolution
- Thin Material - Rad.
Hardness - Large Area
- Power Consum.
- Readout speed -

8
CCD (Charge Coupled Device)
? charge collected in thin layer and transferred
through silicon ? established technology ?
excellent experience at SLD in SLC
300µm ? 40µm
20 x 20 µm2 pixels ? 800 M pixels - SLD
300 M pixels coordinate precision 2-5 µm
- SLD 4 µm
9
CCD Basics
10
CCD Basics
11
CCD ISSUES
CCD classic
? faster readout needed for cold tech (50 µs)
Column-Parallel CCD with low noise -
increase readout cycle of 50MHz
CP CCD
? need radiation hard ?
separate amplifier and readout for each column
bulk damage induced CTI by n and e- being
actively studied with possible countermeasures
- sacrificial charge, faster r/o before
trapping
12
CCD Prototype (LCFI)
CPC1 prototype CP CCD by E2V noise 100
e- CPR1 CP readout ASIC by RAL designed
for 50 MHz 250 parallel
channels CPC1CPR1(bump-bonded) total
noise 140 e- noise from preamps
negligible
noise
radiation effects on fast CCDs detector-scale
CCDs with ASIC and cluster finding logic -
design underway and production this year
5.9 keV(1620e-)
Signal from a 55Fe source observed
13
CCD Radiation Study (KEK))
LED light makes sacrificial charge in CCD. It
fills up traps and improve CTI
VCTI is improved to a half of normal operation
14
CCD Summary
performance proven at SLD good spacial
resolution ( lt 5µm) improve slow readout speed
? 50 MHz CP readout improve the radiation
hardness ? charge injection, notch structure
material reduction with unsupported silicon
15
Image Sensor with In-situ Storage (ISIS)

• 20 readouts/bunch train may be impossible due
  to beam related RF pick up
• motivates delayed operation of detector for long
  bunch train
• charge collection to photogate from 20-30 µm
  silicon, as in a conventional CCD
• signal charge shifted into storage register
  every 50 µs, providing required time slicing
• string of signal charges is stored during bunch
  train in a buried channel, avoiding
  charge-voltage conversion
• totally noise-free charge storage, ready for
  readout in 200 ms of calm conditions between
  trains

16
Monolithic Active Pixel Sensors

• standard CMOS wafer
• charge collection via thermal diffusion
  (no HV)
• in epitaxial layer
• System on Chip possible
• NO bump bonding

10-20µm
17
APS2 chip (UK)

• 4 pixel types, various flavours
• Std 3MOS 3T
• 4MOS (CDS) 4T
• CPA (charge amp)
• FAPS (10 deep pipeline)
• 3MOS and 4MOS 64 x 64,
• 15?m pitch, 8?m epi-layer
• ? MIP signal 600 e-

Design R. Turchetta (RAL)
18
Radioactive source Tests on APS2 structures

• seed pixel
• 3x3 cluster
• 5x5 cluster

Event display
spectrum

• Out of 12 substructures 7 feature a S/N gt 20
• Two structures problems in fabrication
• Bad pixels 1-2
• Preliminary results on irradiation up to 1015
  p/cm2 promising

19
Mimosa prototypes (France)
20
MIMOSA-9
MIMOSA-9 20,30,40 µm pitch with/without 20µm
epi. layer
0.1 X0 layer is achievable in thinning to
50µm - Sensor back-thinned to 15µm
Self-Bias, Pitch 20 ?m, diode 6 x 6 ?m2
21
MIMOSA-9 Results
A promising result since a high eff and a good
resolution for a moderate granularity can not
be for granted.
SB with 20/30 ?m pitch eff 99.8
resolution 1.5 ?m _at_ 20 ?m pitch
22
MAPS Radiation Tolerance
neutron irradiations - fluencies up to 1012
neutrons/cm2 are acceptable with considering
LC requirements of 109 n/ cm2 /year
ionizing irradiations - tests up to a few
100kRad - exact sources of performance losses
are under investigation (diode size and
placements of the transistors are important
parameters)
23
MAPS Summary

• readout and sensor on one chip
• pixel size CCD
• large area sensor and thinning (MIMOSA-9 tested
  OK)
• ? ? gt 99, 20 µm pitch ? ? 2µm
• reasonable radiation hardness
• fast readout (50 MHz possible, MIMOSA6currently
  CDS takes time)
• RD required to bring layer thickness down
• Optimize architecture for LC
• Flexible APS (FAPS) architecture suitable for LC
  and
• fast imaging

24
FAPS

• The in-pixel amp accesses the
• Out line, which is connected to
• all the pixels in a column
• Relatively large capacitive load (gtpF)
• ? Relatively slow

• The in-pixel amp accesses
• only local storage capacitors
• Small capacitive load (ltltpF)
• Write and read phase saparate
• ? Fast

25
FAPS Design (RAL)
26
DEPleted Field Effect Transistor Sensors

• DEPFET detector amplification property
• - high resistivity silicon substrate
• fully depleted by sidewards depletion
• ? full sensitivity over whole bulk
• electrons collected in internal gate and
  modulate
• transistor current
• internal gate can be reset by applying voltage
  to
• a dedicated contact
• ? no reset noise
• - the first amplifying transistors are integrated
• directly into substrate and form pixel structure
• ? a small input capacitance ( 10fF)
• ? very low noise operation can be achieved
• at room temp. (10 e-)

27
DEPFET
DEPFET collaboration Bonn/MPI
p-channel MOS-FETs double pixel structure
(one source two drains) pixel size 20x25µm2
1µm
50 µm
? detector and amplification properties ? fully
sensitivity over whole bulk ? very low noise
operation at room temp.
? readout speed ? ? radiation hardness ? ?
large-area sensor?
28
DEPFET Performance
Excellent noise performance with 55Fe source
spectrum
Single pixel

• Result at Room Temperature
• 131 eV _at_ 5.9 keV
• 2.2 el. r.m.s.

29
? Vertex Detector DEPFET Prototype
thinning process for sensors established
- sensitive area 50µm thinned - fast signal
to cope with high rate requirement -
resolution of 9.5 µm
800x104 mm2
complete clear ? no clear noise - (1 x clear)
then sample 500x in 2.5ms - (clear sample)
500x
for single pixel
30
DEPFET Readout

• system integration of
• a 64x128 pixel matrix
• steering chip (Switchers) tested
• up to 80 MHz
• the read-out chip (the CURO) works
• up to 50/110 MHz (A/D) noise threshold
• dispersion meets the specs
• prototype system with DEPFET CMOS
• matrix is assembled and working
• designing and producing a 512 x 512 matrix
• is planned

row wise selection with Switcher
31
DEPFET Summary
excellent low noise performance at room
temperature low power consumption (saving
material for cooling structure) readout speed
increasing possibilities of thinning the
sensor (20-30 µm) and readout chip
minimize pixel size radiation hardness
32
Vertex Detector Comparison Now
Do not take this seriously. It could be wrong due
to my bias and ignorance!
CCD MAPS DEPFET
Resolution 0
Thin Material - Rad.
Hardness 0 Large Area
? Power Consum.
0 Readout speed 0

33
Summary

• Intensive RD in several VTX technologies
• with good world-wide communication going on!
• Premature choice of technology could seriously
• degrade the physics potential
• Preferred technology(ies) to be selected
• on basis of full-size and fully operational
  prototype ladders
• (when?)

? Time Scale 2004 Cold technology chosen
2005 CDR for ILC (including first cost
estimation) 2007 TDR for ILC 2008
site selection 2009 construction could
start 2015 data taking
34
backups
35
DEPFET Operation Mode

• Pixel array readout scheme
• Individual transistors or
• rows of transistors can be
• selected for readout while the
• other transistors are turned off.
• Those are still able to collect
• signal charge
• fast random access to specific
• array regions
• ? very low power consumption

36
Overview R/O Chip - CURO
CURO CUrrent ReadOut
current based readout ? regulated cascode
fixes input node

• algebraic operations easy in current mode !
• automatic pedestal subtraction (fast CDS)
• on chip hit detection and zero suppression
• analog r/o of hits

CURO I prototype chip (05/2002)

• Main parts
• current memory cells
• current comparator
• hit finder

CURO II 128 channel r/o chip
(11/2003)