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• Silicon Programming
• programmable logic
• Altera devices and the Altera tools
• major tasks in the silicon programming process
• using a .vec file for testing
• (note references are to textbook by Hamblen et
  al)

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LE (Logic Element)
LAB (Logic Array Block)
RAM Block
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• Device families
• Example Cyclonewe will use EP1C6 or EP1C2
• features
• logic elements (LEs)
• RAM blocks
• Global clock Phase locked loops for clock
  configuration
• gt 170 I/O pins
• Cyclone LEfigure 3.7
• Cyclone LABs and interconnects figure 3.9

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• Example using a lookup table to describe a gate
  network
• f(A,B,C) A'B'C A'BC' A'BC ABC
• Inputs ABC out
• 000 0
• 001 1
• 010 1
• 011 1
• 100 0
• 101 0
• 110 0
• 111 1

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• Other common architectures
• Product Term CPLD Altera MAX 7000S
• uses matrix of produce terms can expand to
  neighboring macrocells
• Figures 3.5, 3.6
• Configurable logic blocks (CLB) Xilinx 4000
• Figure 3.12

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VGA port
UP3 BOARD
parallel port
PS2 port
Cyclone chip
USB port
SRAM
serial port
FLASH
invalid input voltage LED
on/off switch
user-definable pushbuttons
user-definable LEDs

• power

3.3V supply LED
user-definable DIP switches
5V supply LED
global reset
LC Display
http//users.ece.gatech.edu/hamblen/UP3/
and http//users.ece.gatech.edu/hamblen/UP3/UP32
0Reference20Manual.pdf
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• Technology SRAM
• General description
• http//en.wikipedia.org/wiki/Static_Random_Access_
  Memory
• General information on programmable devices
• http//www.tutorial-reports.com/computer-science/f
  pga/user-programmability.php

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