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1
Altera Training Course
2
Agenda

• Introduction
• Device Architecture
• MAX 7000 / MAX 9000 / MAX 3000 Family
• FLEX 8000 / FLEX 10K / FLEX 6000 Family
• APEX Family
• MAXPLUS II Design Flow
• Design
• Compilation
• Simulation
• Timing Analysis
• Programming
• Others (Floorplan Editor)

3
Altera General-Purpose Logic Devices
CMOS PLDs
Simple PLDs
High-Density PLDs
FPGAs
CPLDs
FLEX FLEX10K FLEX8000
FLEX6000
APEX APEX 20K
Xilinx Lucent Quicklogic Actel
MAX 9000 MAX 7000 MAX 5000 Classic
4
Introduction to Altera

• Inventor of the CPLD in 1983
• Products Families
• Product Term-based (EPROM, EEPROM)
• MAX 7000
• MAX 9000
• Look-Up Table-based (SRAM)
• FLEX 10K
• FLEX 8000
• FLEX 6000
• LUT P-Term Memory(SRAM)
• System-on-a-Programmable-Chip
• APEX 20K

5
Altera Device Terminology

• Logic Cell
• The basic building block of an Altera device
• Macrocell
• The basic building block of Product Term-based
  device
• MAX9000, MAX7000, MAX5000, Classic
• Logic Element
• The basic building block of Look-Up Table-based
  device
• FLEX10K, FLEX8000, FLEX6000
• Logic Array Block(LAB)
• A collection or group of logic cells

6
Product Term-Based Building Blocks

• Programmable-AND, Fixed-OR Array
• XOR Gate for Synthesis or Inversion
• Capacity Limited by Number of Product Terms
• High Number of Inputs

7
Look-Up Table-Based Building Blocks

• An n-input LUT Can Implement Any Function of n
  Inputs (e.g., n-Input AND, n-Input XOR)
• Functions Equations with More than n Inputs Are
  Split between LUTs

Input 1
Black Box LUT
Input 2
Output
Input 3
Input 4
8
Which PLD Should I Use?
Product Term Architecture
Look-Up Table Architecture

• Complex Combinatorial Logic
• Complex State Machines
• Control-Intensive Logic
• Fully Encoded State Machines
• High Fan-In
• Examples
• Memory Bus Controller
• Decode Logic

• Datapath Functions
• Register-Rich Designs
• Arithmetic Functions
• Adders, Counters, etc.
• One Hot Encoded State Machines
• Examples
• DSP Functions
• PCI Interface

Alteras Solution
MAX
FLEX
9
MAX 7000 Device Technology

• Multiple Array MatriX (MAX) devices
• programmable - AND / fixed - OR product term
  architecture
• Altera MAX 7000 devices include
• MAX 7000
• MAX 7000E
• MAX 7000S
• MAX 7000A
• MAX 7000B
• EPLDs fabricated on CMOS process
• EEPROM configuration elements (non-volatile)

10
MAX 7000(E)(S) Family

• Features ...
• High-performance, mid-density EPLD standard
• 32 256 macrocells, 600 5,000 usable gates
• 5 V MAX 7000(E) devices and 5 V ISP MAX 7000S
• In-System Programmability(ISP) in MAX 7000S
• Built-in JTAG BST circuitry in MAX 7128S or above
• 5 ns pin-to-pin delays with up to 175.4 MHz
  counter frequency
• PCI-compiliant devices available
• Open-drain output option in MAX 7000S
• Programmable macrocell flipflops with individual
  clear, preset, clock, and clock enable controls
• Programmable power-saving mode for a reduction of
  over 50 in each macrocell

11
MAX 7000(E)(S) Family

• More Features ...
• Allowing up to 32 product terms per macrocell
  using expander
• Programmable security bit for protection of
  designs
• 3.3 V or 5 V MultiVolt I/O interface
  operation(above 68-pin packages)
• Non-E Versions for Smaller Devices
  (7032,7064,7096)
• E Versions for Larger Devices (7128, 7160, 7192,
  7256)
• S Versions for All Devices
• Enhanced features in MAX 7000E and MAX 7000S
• More Output Enable Control Signals(6 Pin/Logic
  Driven vs. 2 Pin)
• More Global Clock signals with optional
  inversion(2 Global Clocks vs. 1)
• Enhanced interconnect resources for improved
  routability
• Fast input registers
• Programmable output slew-rate control

12
MAX 7000 Family
EPM7032
EPM7128E
EPM7256E
EPM7064
EPM7032V
EPM7128S
EPM7256S
EPM7160E
EPM7192E
EPM7384AE
EPM7512AE
EPM7064S
Feature
EPM7096
EPM7032S
EPM7128A
EPM7256A
EPM7160S
EPM7192S
EPM7384B
EPM7512B
EPM7064AE
EPM7032AE
EPM7128AE
EPM7256AE
EPM7064B
EPM7032B
EPM7128B
EPM7256B
Macrocells
32
64
96
128
160
192
256
384
512
Usable Gates
600
1250
1800
2500
3200
3750
5000
7500
10000
Flipflops
32
64
96
128
160
192
256
384
512
13
Device Part Numbers

• EPM7128ATC144-6
• EPM Family Signature (Erasable Programmable MAX
  device)
• 7128A Device type (128 number of macrocells)
• T Package type (L PLCC, T TQFP...)
• C Operating temperature (Commercial,
  Industrial)
• 144 Pin count (number of pins on the package)
• -6 Speed Grade (-5, -6, -7, -10, -12, -15)
• Suffix may follow speed grade (for special device
  features)
• Another Example
• EPM7064SLC44-5
• EPM7064S in a commercial-temp, 44 pin PLCC
  package with a 5 ns speed grade

14
Device Block Diagram
I/O Control Block
4 dedicated inputs drive PIA, Macrocells, I/O
Control Block
36
36
16Macro-cells
16Macro-cells
16
16
PIA
3 to 16
3 to 16
36
36
16Macro-cells
16Macro-cells
16
16
3 to 16
3 to 16
3 to 16 fast input paths MAX 7000E/S/A/B devices
only
3 to 16 I/O pins
Logic Array Block (LAB)
15
MAX 7000/E/S Macrocell
Global Clock(s) MAX 7000 -gt 1
MAX 7000E/S -gt 2
LAB Local Array
GlobalClear
Parallel Expanders from other macrocells
From I/O Pin
Fast Input Select -gt MAX 7000E/S only
Register Bypass
To I/O Control Block
PRN
Q
D
Product-Term Select Matrix
EN
CLRN
Clock/ Enable Select
Clear Select
Shareable Logic Expanders
To PIA
16 shared expander product terms
16
Logic Array Block
INPUT
GCLK1
INPUT
GCLK2
GCLR
INPUT
GOE
INPUT
36
3 to 16 fast input paths MAX 7000E/S/A/B devices
only
16
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
3 to 16
LAB Local Array
Macrocell 8
Macrocell 9
Macrocell 10
Macrocell 11
3 to 16 I/O pins
Macrocell 12
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
16
17
MAX 7000E/S/A/B MAX 7000
GCLK1
GCLK1
INPUT
INPUT
OE1n
OE2/GCLK2
INPUT
INPUT
OE2n
GCLRn
INPUT
INPUT
OE1
GCLRn
INPUT
INPUT

• 4 Dedicated Inputs can drive
• any macrocell control signal (clock, clear,
  preset, enable)
• data
• any combination of above (if the input drives a
  control signal as well as different type of
  control signal or data then the control signal
  will be non-global)

LAB Local Array
6 to 16 I/O pins
18
Expanders
LAB Local Array
Parallel Expanders from other macrocells
Expanders are used to create logic functions
requiring more resources than in a single
macrocell
Product-Term Select Matrix
Shareable Logic Expanders
When expanders are needed to implement a logic
function, shared expanders are automatically used
by default
16 shared expander product terms
19
Shareable Logic Expanders

• Each macrocell can donate one product term as a
  shared expander instead of using it as a standard
  product term
• Each LAB can have up to 16 shared expanders that
  can be used by any or all macrocells in the LAB
• LAB Local Array

Macrocell Product- Term Logic
ù

ù
ù
Macrocell Product- Term Logic
ù
ù
ù
20
Parallel Expanders
From previous macrocell

• Parallel expanders are unused product terms that
  can be allocated to neighboring macrocells

Preset
Product-Term Select Matrix
parallel expanders
GND
Clock
Clear

• Parallel expanders implement faster complex logic
  functions

Preset
Product-Term Select Matrix
To next macrocell
GND
Clock
LAB Local Array
Clear
21
Parallel Expanders vs. Shareable Expanders
22
MAX 7000 I/O Control Block
VCC
OE1
OE control
OE2
GND
from Macrocell
to PIA
23
MAX 7000E/S I/O Control Block
6 Global OEs
PIA
VCC
OE control
GND
from Macrocell
Open-Drain (MAX 7000S devices only)
Slew-Rate Control
Fast Input to Macrocell Register
to PIA
24
Special Features

• Programmable Speed/Power Control
• Each Macrocell Can Be Programmed for Either High
  Speed (Turbo Bit on) or Low Power (Turbo Bit off)
• Slew-Rate Control
• MAX 7000E MAX 7000S Output Buffers Have an
  Adjustable Output Slew Rate that Can Be
  Configured for Low-Noise or High-Speed
  Performance
• Open-Drain Output Option
• Each MAX 7000S I/O Pin Can Provide an Open-Drain
  Output

25
MAX7000A

• Features...
• 32 512 macrocell, 6000 10,000 usable gates
• 3.3V in-system programmability(ISP) -
• Built in JTAG boundary-scan test(BST) circuitry
• Enhanced ISP features in MAX 7000AE
• Enhanced ISP algorithm for faster programming
• ISP_Done bit to ensure complete programming
• Pull-up resistor on I/O pins during ISP
• 4.5 ns pin-to-pin delays with up to 192.3 MHz
  counter freq.
• Hot-socketing in MAX 7000AE
• Programmable power-up states for macrocell
  register in MAX 7000AE
• Programmable power-saving mode

26
MAX7000A

• More Features...
• Programmable security bit
• 6 to 10 pin or logic driven output enable signals
• Two global clock signals with optional inversion
• Fast input registers
• Programmable output slew-rate control
• Programmable ground pins
• PCI compliant
• Open-drain output option
• MultiVolt I/O interface with 2.5V, 3.3V, 5V

27
MAX 9000 Family

• Features...
• High performance and high density EPLD
• 320 560 macrocells, 6,000 12,000 usable gates
• 5 V ISP via built-in JTAG interface
• Dual-output macrocell for independent use of
  combinatorial and registered logic
• FastTrack Interconnect
• Input/Output registers on all I/O pins
• 10 ns pin-to-pin delays up to 144 MHz counter
  frequency
• PCI compliant (-12 speed grade)
• 3.3V or 5 V I/O operation/MultiVolt I/O interface
• Programmable output slew-rate control

28

MAX 9000 Family
EPM9320
EPM9560
Feature
EPM9400
EPM9480
EPM9320A
EPM9560A
Macrocells
320
400
480
560
Usable
6,000
8,000
10,000
12,000
Gates
Flipflops
484
580
676
772
Note Use Alteras web site to check device and
package availability http//www.altera.com
29
MAX 9000 Device Block Diagram
4 dedicated inputs drive FastTrack
Interconnect, Macrocells, I/O Cells
10 IOCs at the end of each Column
8 IOCs at the end of each Row
FastTrack Interconnect
Logic Array Block (LAB)
30
MAX 9000 Logic Array Block
DIN1
GCLK1
DIN2
GCLK2
GCLR
DIN3
To peripheral control bus
GOE
DIN4
Row FastTrack Interconnect
33
16
16
Column FastTrack Interconnect
Macrocell 1
48
16
Macrocell 2
Macrocell 3
Each macrocell can drive both the Row and Column
Interconnect at the same time
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
LAB Local Array
Macrocell 8
48
16
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
16
16
31
MAX 9000 Dedicated Inputs

DIN1
GCLK1
DIN2
GCLK2
GCLR
DIN3
GOE
To peripheral control bus
DIN4
Row FastTrack Interconnect
33
16
16
Macrocell 1
48
16
Macrocell 2
Macrocell 3
Column FastTrack Interconnect
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
LAB Local Array
Macrocell 8
48
16
Macrocell 9
Macrocell 10
Macrocell 11
Macrocell 12
Macrocell 13
Macrocell 14
Macrocell 15
Macrocell 16
16
16
32
MAX 9000 Dedicated Inputs

• 2 Dedicated Global Clock Inputs Can Drive
• Any Macrocell Control Signal (Clock, Clear,
  Preset, Enable)
• Clock Signals on Peripheral Control Bus
• Data
• Any Combination of Above (Non-Global Signal Use
  May Result)
• 1 Dedicated Global Clear Input Can Drive
• Any Macrocell Control Signal (Clock, Clear,
  Preset, Enable)
• Clear and Clock Enable Signals on Peripheral
  Control Bus
• Data
• Any Combination of Above (Non-Global Signal Use
  May Result)
• 1 Dedicated Global OE Input Can Drive
• Any Macrocell Control Signal (Clock, Clear,
  Preset, Enable)
• Output Enable, Clock Enable, and Clear Signals
  on Peripheral Control Bus
• Data
• Any Combination of Above (Non-Global Signal Use
  May Result)

• Peripheral control bus signals drive I/O Cells
  (IOCs)
• Data loading on non-global signals will add
  delay

33
MAX 9000 Macrocell
Parallel Expanders from other macrocells
33 Row FastTrack Interconnect inputs
Global Clear
Global Clocks
LAB Local Array
This path from P-Term Select Matrix supports
register packing
2
To FastTrack Interconnect
PRN
Q
D
Product-Term Select Matrix
EN
CLRN
Local Array Feedback
Clock/ Enable Select
Clear Select
Shareable Logic Expanders
16 local feedbacks
16 shared expander product terms
34
Register Packing
Combinatorial Function

• The macrocells combinatorial and registered
  functionality is used independently (dual output)
  
• This feature can be turned on or off through a
  Logic Option in MAXplus II

XOR
p-term Clock
XOR
p-term Clear
p-term Preset
To FastTrack Interconnect
Registered Function
p-term Preset
Single p-term Input
Q
D
EN
Global Clock
CLRN
p-term Clock
To Local Feedback
VCC
p-term Clear
35
MAX 9000 I/O Cell
Peripheral Control Bus 12..0
VCC
OE7..0
8
to Row or Column FastTrack Interconnect
13
from Row or Column FastTrack Interconnect
D
Q
Slew-Rate Control
CLK3..0

4
VCC
ENA
CLRN
ENA5..0
VCC
6
CLR 1..0
2
36
I/O Cell Register
Peripheral Control Bus 12..0
VCC
OE7..0
to Row or Column FastTrack Interconnect
8
13
from Row or Column FastTrack Interconnect
D
Q
CLK3..0
The I/O cell register can be used for fast setup
times (tSU) or fast clock to out times (tCO)

4
VCC
ENA
CLRN
ENA5..0
VCC
6
CLR 1..0
2
37
Output Enables
VCC
Peripheral Control Bus 12..0
OE7..0
8
13
D
Q
Slew-Rate Control

• Available Output Enables
• Up to 8 OE signals (including the dedicated OE
  input) from the Peripheral Control Bus

38
Slew-Rate Control
Peripheral Control Bus 12..0
VCC
OE7..0
8
to Row or Column FastTrack Interconnect
13
from Row or Column FastTrack Interconnect
D
Q
When Slow Slew Rate is selected, board-level
noise is reduced and a timing delay is added to
the output buffer delay parameter Compare tOD1,
tOD2, tOD3 in the Data Book
Slew-Rate Control
39
FLEX 8000 Family

• Features...
• Low-cost, high-density, register-rich(282
  1,500)
• 208 1,296 Logic Elements, 2,500 16,000 usable
  gates
• In-Circuit Reconfigurability(ICR)
• Built-in JTAG BST circuitry
• PCI compliant
• Programmable output slew-rate control
• I/O registers for fast setup and clock-to-output
  delay
• 3.3V or 5.0V operation
• Four global inputs with inversion capability
• FastTrack Interconnect continous routing
  structure
• Dedicated carry and cascade chain

40
FLEX 8000 Devices
Max. Usable Gates Logic Elements Registers Max.
User I/O JTAG BST Packages
Refer to www.altera.com for latest packaging
information
All Devices Except The EPF8452A And
EPF81188A Have JTAG BST Circuitry
41
FLEX 8000 Block Diagram
4 Dedicated Inputs
I/O Element(IOE)
RowFastTrackInterconnect
Logic ArrayBlock
LogicElement
LocalInterconnect
ColumnFastTrackInterconnect
42
FLEX 8000 Dedicated Inputs

• 4 Dedicated Inputs Drive 4 Global Control Nets
  that Can Drive
• Any LE Register Control Signal (Clock, Clear)
• Any Signal (Clock, Clear, Output Enable) on
  Peripheral Control Bus
• Peripheral Control Bus Controls I/O Elements
  (IOE)
• Data
• Any Combination of Above

43
FLEX 8000 LAB
Dedicated Inputs
Row Interconnect
LAB Local Interconnect
LAB Control Signals
Column Interconnect
44
FLEX 8000 Logic Element
Carry-In
Cascade-In
To Row, Column, LAB Local Interconnects
DATA1
Look-Up Table (LUT)
Carry Chain
PRN CLRN
Cascade Chain
DATA2
D
Q
DATA3
DATA4
Clear/ Preset Logic
LAB Clear/ Preset 1
LAB Clear/ Preset 2
Clock Select
LAB Clock 1
LAB Clock 2
Carry-Out
Cascade-Out
45
Architecture Features

• Controlling These Features Controls
  DesignImplementation, Performance Utilization
• Carry Chain
• Arithmetic Functions
• Cascade Chain
• Wide Fan-in Functions

46
Carry Chain
Implements fast adders, counter and comparators
47
Cascade Chain
Cascades LUT Outputs, Implementing
High-Performance, Wide Fan-in Functions
LE
LUT
in3..0
LE2
LUT
in7..4
LEn
LUT
Result of Inputs in0 to 4n-1
in4n-1 .. 4(n-1)
48
Cascade Chain Example
Without Cascade Chains 3 LEs
Using Cascade Chains 2 LEs
LE
in3..0
LUT
LE2
in7..4
LUT
result
49
Carry and Cascade Chain Construction

• Begins in First LE (LE1) of Every LAB
• Functions Carry Chain Can Begin in Any LE of an
  LAB
• Runs Downward through LEsof a LAB

• At End of LAB, carry chain continues to Top of
  Next LAB in Same Row
• Stops at End of Row

50
Using Carry Chains in Your Design

• Number of Chains
• No More Than 20 of FLEX Device Should Use Carry
  Chains
• Length of Each Chain
• Maximum Length Should Be 32 LEs for Performance
• For Ripple-Carry Longer than 32 LEs, Consider
  Carry Look-Ahead or Carry-Select Implementations
  to Improve Performance
• Carry Chains Longer Than 32 LEs May Still Provide
  Utilization Advantages
• Further Reading
• AN 36 Designing with FLEX 8000 Devices
• MAXPLUS II Online Help Search on Carry

51
Using Cascade Chain

• Cascade Chains Can Improve Density, Performance
• LEs Locked Together, Challenging Fitting of Logic
• Recommendations
• No More Than 20 of the FLEX Device Should Use
  Cascade Chains
• Maximum Length Should Be 2 LEs for Performance
• Cascade Chains Longer Than 2 LEs May Still
  Provide Utilization Advantages
• Further Reading
• AN 36 Designing with FLEX 8000 Devices
• MAXPLUS II Online Help Search on Cascade

52
Synthesis Styles FLEX Features

• NORMAL

• FAST

• WYSIWYG

53
FLEX 8000 IOE
54
FLEX 6000

• Features...
• Register-rich, LUT-based, OptiFLEX architecture
• 800 1960 LEs, 10000 24000 gates
• Low-cost alternative to gate arrays for
  high-volume production
• Built-in low-skew clock distribution tree
• Built-in JTAG circuitry
• MultiVolt I/O
• PCI compliant
• Individual tri-state output enable control for
  each pin
• 3.3 V devices support hot-socketing

55
FLEX 6000 Devices
EPF6016 EPF6016A
EPF6010A
EPF6024A
Max. Usable Gates Logic Elements Registers Max.
User I/O Packages
16,000 1,320 1,320 204
10,000 880 880 139
24,000 1,960 1,960 218
Refer to www.altera.com for latest packaging
information
All Devices Have JTAG BST Circuitry
56
FLEX 6000 Block Diagram
4 Dedicated Inputs
Chip-Wide Reset
Output Enable
Column Interconnect
IOE
Row Interconnect
LAB
LAB Local Interconnect
57
FLEX 6000 Global Nets

• 4 Global Control Nets Designed for High Fan-out
  Signals
• Any Register Control Signal (Clock, Clear)
• Data
• Combination of Data Register Control Signals
• Global Control Nets Can Be Driven by
• Dedicated Inputs
• Internal Logic

58
FLEX 6000 LAB
Row Interconnect
Global Nets
LAB Local Interconnect
LAB Local Interconnect
LAB Control Signals
LEs 1-5
LEs 6-10
59
FLEX 6000 LAB Control Signals
4
Global Nets
LAB Local Interconnect
data1
LAB Clock 1
LE1
data2
LAB Clock 2 Synchronous Load
data3
LAB Clear/Preset 1
data4
LAB Clear/Preset 2 Synchronous Clear

• Each LAB Supports
• For Registers
• 2 Clock Signals
• 2 Clear/Preset Signals

• For Counters Using Carry Chains
• Synchronous Load
• Synchronous Clear

60
FLEX 6000 Logic Element
Carry-In
Cascade-In
DATA1
Look-Up Table (LUT)
Carry Chain
PRN CLRN
Cascade Chain
DATA2
LE Out
D
Q
DATA3
DATA4
LAB Clear/ Preset 1
Clear/ Preset Logic
LAB Clear/ Preset 2
Chip-Wide Clear
Clock Select
LAB Clock 1
LAB Clock 2
Carry-Out
Cascade-Out
61
Architecture Features
User-Controlled Architectural Features Affects
Performance Utilization

• Carry Chain
• Arithmetic Functions
• Cascade Chain
• Wide Fan-in Functions

These Features Are Controlled Using

• Logic Options
• Synthesis Styles

62
LE-to-LE Connection LAB Interconnect Only
LEs of Adjacent LABs Can Communicate through
Their Shared LAB Local Interconnects Provides
a Very Fast Path (See Appendix Local Routing)

• LEs 1-5 Drive to the Right LEs 6-10 Drive to the
  Left
• LEs Are Driven by Both Adjacent LAB Local
  Interconnects
• Data Inputs 2 4 Come from the Right
• Data Inputs 1 3 Come from the Left
• Any Channel of a LAB Local Interconnect Can Drive
  Any LEs of an Adjacent LAB

LEs 1-5
LEs 1-5
LAB Local Interconnect
LAB Local Interconnect
LAB Local Interconnect
5
5
LEs 6-10
LEs 6-10
10
10
10
10
63
Row Outputs
Any LE Can Drive through Row or Column
Interconnect to Any IOE
Row Interconnect
10 IOEs at End of Each Row
LAB Local Interconnect
LAB
10
Each IOE Is Driven by Any Channel in Adjacent LAB
Local Interconnect
All 10 LEs in Row-End LABs Can Drive Row IOEs
through Adjacent LAB Local Interconnect for Fast
Clock-to-Output
64
FLEX 6000 IOE
Delay
to Row or Column Interconnect
Chip-Wide Output Enable
VCC
from LAB Local Interconnect
VCC
I/O Pin
from LAB Local Interconnect
Slew-Rate Control (Selectable per Pin)
Open-Drain Output (Selectable per Pin)
65
FLEX 10K Family

• Features...
• Industrys first embedded array PLD(memory
  function)
• 10,000 250,000 typical gates
• 6,144 40,960 RAM bits (10K, 10KA)
• 24,576 98,304 RAM bits(10KE)
• ICR, built-in JTAG, PCI compliant
• MultiVolt I/O interface support
• ClockLock and ClockBoost option for reduced clock
  delay/skew and clock multiplication
• Pull-up clamping diode for 3.3 V PCI compliance
• Individual tri-state output enable control for
  each pin
• Open-drain option on each I/O pin
• Programmable ouptut slew-rate control
• Hot-socketing support (10KA, 10KE)

66
FLEX10K family

• Various supply voltage, family
• -- 10K -- 5 V ( 10,000 100,000 typical gate)
• -- 10KA -- 3.3 V ( 10,000 250,000 typical
  gate)
• -- 10KV -- 3.3 V ( 50,000 , 130,000 typical
  gate)
• -- 10KE -- 2.5 V ( 30,000 200,000 typical
  gate)
• MultVolt interface
• -- 10K -- 3.3V, 5V interface
• -- 10KA -- 2.5V, 3.3V, 5V interface
• -- 10KV -- 3.3V , 5V interface
• -- 10KE -- 2.5V, 3.3V, 5V interface

67
FLEX 10K/V/A/B Devices
All Devices Have JTAG BST Circuitry (IEEE Std.
1149.1-1990 Compliant) Available at No Logic
Cost Refer to www.altera.com for Latest
Packaging Information
68
FLEX 10KE Devices
All Devices Have JTAG BST Circuitry (IEEE Std.
1149.1-1990 Compliant) Available at No Logic
Cost Refer to www.altera.com for Latest
Packaging Information
69
FLEX 10K Family Block Diagram
Chip-Wide Reset, Chip-Wide Output Enable
4 Dedicated Inputs, 2 Dedicated Clocks
Peripheral Control Bus
RowFastTrackInterconnect
Embedded Array Block (EAB)
Logic ArrayBlock
I/O Element(IOE)
Embedded Array Block (EAB)
LogicElement
LocalInterconnect
ColumnFastTrackInterconnect
70
Dedicated Inputs, Clocks

• 4 Dedicated Inputs Drive 4 Global Control Nets
  that Can Drive
• Any LE Control Signal (Clock, Clear, Enable)
• Four Nets of the Peripheral Control Bus(Clock,
  Clear, Output Enable)
• Data
• Any Combination of Above
• 4 Global Control Nets Can Also Be Driven by
  Internal Logic
• 2 Dedicated Clocks Drive 2 Global Clock Nets that
  Can Drive
• LE Clock Signals
• IOE Clock Signals
• Data
• Any Combination of Above
• Cannot Serve as Any Other Control Signal

71
FLEX 10K Family LAB
Global Control Nets, Dedicated Clocks
Row Interconnect
Column Interconnect
LAB Local Interconnect
LAB Control Signals
72
FLEX 10K Family LAB Control Signals

• Each LAB Supports for its Registers
• 2 Clock Signals
• 2 Clear/Preset Signals

73
FLEX 10K Family Logic Element
Multiplexer for Register Packing
Carry-In
Cascade-In
DATA1
Look-Up Table (LUT)
Carry Chain
To Row, Column Interconnects
PRN CLRN
Cascade Chain
DATA2
D
Q
DATA3
DATA4
ENA
Clear/ Preset Logic
To LAB Local Interconnect
LAB Clear/ Preset 1
LAB Clear/ Preset 2
Chip-Wide Reset
Clock Select
LAB Clock 1
LAB Clock 2
Carry-Out
Cascade-Out
74
Architecture Features

• Controlling These Features Controls Design
  Performance Utilization
• Register Packing
• Allows Using LUT Register of Same LE Separately
  
• Carry Chain
• Arithmetic Functions
• Cascade Chain
• Wide Fan-in Functions
• Features are Controlled through MAXplus II

75
Register Packing
Multiplexer for Register Packing
Carry-In
Cascade-In
DATA1
Look-Up Table (LUT)
Carry Chain
To Row, Column Interconnects
PRN CLRN
Cascade Chain
DATA2
D
Q
DATA3
DATA4
ENA
Clear/ Preset Logic
To LAB Local Interconnect
LAB Clear/ Preset 1
LAB Clear/ Preset 2
Chip-Wide Reset

• Allows LUT Register of a LE to Be Used
  Separately
• Can Improve Utilization

Clock Select
LAB Clock 1
LAB Clock 2
Carry-Out
Cascade-Out
76
Carry Chain
Carry-In
Cascade-In
DATA1
Look-Up Table (LUT)
Carry Chain
To Row, Column Interconnects
PRN CLRN
Cascade Chain
DATA2
D
Q
DATA3
DATA4
ENA
Clear/ Preset Logic
To LAB Local Interconnect
LAB Clear/ Preset 1
LAB Clear/ Preset 2
Chip-Wide Reset
Clock Select
LAB Clock 1
LAB Clock 2
Carry-Out
Cascade-Out
77
Cascade Chain
Cascades LUT Outputs, Implementing
High-Performance, Wide Fan-in Functions
LE
LUT
in3..0
LE2
LUT
in7..4
LEn
LUT
Result of Inputs in0 to 4n-1
in4n-1 .. 4(n-1)
78
I/O Element
79
EAB

• A Large Block of Embedded RAM
• 10K/V/A/B - 2048 Bits, Single-Port RAM
• 10KE - 4096 Bits, Dual-Port RAM

EAB
EAB
80
Available RAM in FLEX 10K Family Devices
One EAB per Row in all FLEX 10K Family Devices
RAM Bits
Device Rows 10K/V/A/B 10KE
EPF10K10/A 3 6,144 EPF10K20 6 12,288 EPF10K30/A/
E 6 12,288 24,576 EPF10K40A 8 16,384 EPF10K50/V/A
/E 10 20,480 40,960 EPF10K70 9 18,432 EPF10K100/A
/B/E 12 24,576 49,152 EPF10K130/V/E 16 32,768 65,5
36 EPF10K200E 24 98,304 EPF10K250A/E 20 40,960 81
,920
81
EAB

• EAB Can Be Configured Four Ways

FLEX 10K/V/A/B EAB 2,048 Bits RAM
FLEX 10E EAB 4,096 Bits RAM
256 x 8 512 x 4 1,024 x 2 2,048 x 1
256 x 16 512 x 8 1,024 x 4 2,048 x 2
82
Cascading EABs for Memory

• EABs Cascaded to Create Wider RAM
• EABs Cascaded, Multiplexed to Create Deeper RAM
• No Speed Penalty up to
• 10K/V/A/B - 2,048 Bits Deep
• 10KE - 4,096 Bits Deep
• MAXplus II Configures RAM in Fastest Way Possible

256 x 16
256 x 32
256 x 16
83
FLEX 10K/V/A/B EAB
RAM/ROM 2,048 Bits
1, 2, 4, 8
1, 2, 4, 8
D
Data In
D
Data Out
11, 10, 9, 8
Address
D

• EAB contains registers for incoming and outgoing
  signals

256 x 8 512 x 4 1,024 x 2 2,048 x 1
Write Enable
D
Write Pulse Circuit
In Clock
Out Clock
84
10KE EAB
Data Out
D ENA
RAM/ROM 4,096 Bits
Data In
D ENA
Write Address
D ENA
256x16 512x8 1024x4 2048x2
Write Enable

• EAB contains registers for incoming and outgoing
  signals

D ENA
Read Address
D ENA
Read Enable
D ENA
Clock 1
Clock 1 Enable
Clock 2
Clock 2 Enable
85
MAXplus IIs MegaWizard

• Memory Elements are Created with MAXplus IIs
  MegaWizard Manager

• Dual-Port RAM
• FIFO
• LPM_FF
• LPM_LATCH
• LPM_RAM_DQ
• LPM_RAM_IO
• LPM_ROM
• LPM_SHIFTREG

86
MegaWizard Manager Output

• Selection of Output Files
• AHDL File
• VHDL Component to Instantiate
• Verilog Component to Instantiate
• Automatically Generated
• Symbol for Schematic
• Include File

87
Memory Elements and Implementation

• Elements Implemented in LEs
• LPM_FF - An Array of D Flip-Flops (DFFEs in LEs)
• LPM_LATCH - An Array of Latches (LUTs in LEs)
• LPM_SHIFTREG - Shift Register
• Elements Implemented in LEs and/or EABs
• Dual-Port RAM
• FIFO
• LPM_RAM_DQ (Separate Read Write Data Ports)
• Recommended over LPM_RAM_IO
• LPM_RAM_IO (Single, Bi-directional Data Port)
• LPM_ROM

88
Use of EAB

• Logic Functions
• Area-efficient and fast for complex functions
• DSP
• Arithmatic Logic
• Microprocessor / Microcontroller
• Memory Functions
• RAM
• ROM
• Dual-port RAM
• FIFO

89
APEX 20K Quartus Overview
90
The Best of All Worlds

• FLEX 10K
• Interconnect
• Embedded Memory
• High Density
• Phase-Locked Loop

• MAX 7000
• Product Terms
• Wide Fan-in
• Fast State Machines

APEX 20K

• FLEX 6000
• Interleaved LABs
• LE Structure
• I/O Structure

91
APEX 20K Features

• 125-MHz System Performance
• 64-Bit, 66-MHz PCI Compliance
• 4-Level Continuous FastTrack Interconnect
• New Level of Routing Hierarchy
• Enhanced Phase-Locked Loop (PLL)
• Advanced I/O Standard Support
• Includes SSTL-3, GTL, LVDS, and More
• MultiVolt I/O Interface
• Advanced FineLine BGA Packaging

92
APEX 20K Devices
93
APEX 20K Supply Voltage
2.5 VCore VCC 0.25/0.22 µ
1.8 V Core VCC 0.18 µ
94
MultiCore Architecture
95
FineLine BGA Efficiency
Area 100-Pin TQFP
96
SameFrame Pin-Out Advantage
484-Pin FineLine BGA
256-Pin FineLine BGA
97
Embedded System Block
ESB
98
APEX 20K I/O Features

• Supports Multiple I/O Standards
• LVTTL, LVCMOS
• GTL, CTT, AGP
• HSTL, SSTL-2, SSTL-3
• LVDS
• Hot Socketing Support
• MultiVolt Support for 1.8-, 2.5-, 3.3-V Devices
• Pin-by-Pin Selectable 3.3-V PCI Clamp

99
APEX 20KE I/O Blocks
100
SignalTap Logic Analysis
Embedded Logic Analysis
101
SignalTap Plus
102
Embedded Product-Term Performance
8.6 ns
4.8 ns
103
Quartus Development System
104
Streamlined Design Flow

• Workgroup Computing
• NativeLink Integration with EDA Tools
• Scripting
• Incremental Compilation
• Easy Floorplanning Linked to Design
• Intellectual Property

105
Additional Quartus Features

• Verification
• Native HDL Simulator / Timing Analyzer
• SignalTap Hardware Verification at Speed
• Internet-Based Support
• Device Support Updates
• Patch Notification
• Quick Solutions
• Enhancement Requests
• Software Problem Reporting/Tracking

106
8-Port, 100-Mbit Ethernet Switch
32 Bit, 64 MHz
In FIFO
16-to-32 Bit Interface
100 MBit MAC Interface
Message Memory 96MB
Out FIFO
Write Memory Control
SSTL-3
Port 1
PLL
SSTL-3
Read Memory Control
In FIFO
16-to-32 Bit Interface
100 MBit MAC Interface
Out FIFO
Memory Controller
Port 8
CAM
System Memory
GTL
RISC µP
FIFO
Cache Memory
LVTTL
FIFO
Usage Parameter Control S/M
32-Bit, 33-MHz PCI
Diagnostic Interface
32 Bit, 33 MHz
107
8-Port, 1-Gbit Ethernet Switch
108
APEX 20K Quartus Summary

• Revolutionary Architecture for Integration
• Quartus Speeds Complex Designs to Market
• 1-Gbit Ethernet Switch Illustrates Capabilities

109
Altera MAXPLUS II Development System
110
MAXPLUS II Design Flow
Design Entry
Compilation
Simulation
Timing Analysis
Device Programming
111
MAXPLUS II Advantages

• Fully Integrated, Single Interface
• Extremely Easy to Learn Use
• Runs on Multiple Platforms
• Windows 3.1, Windows 95, Windows NT
• HP 9000 Series 700
• IBM RISC System/6000 Workstations
• Sun SPARCstation
• Provides All Tools Needed for Complete PLD
  Project Cycle
• Extremely Fast Performance!

112
Altera Design Methodology

• Hierarchical Design Management
• Top-down Bottom-up Approaches
• Different Design Entry Can Be Used for Same
  Design
• Use Megafunctions/LPM
• Create Lower-Level Designs (Macrofunctions) for
  Different Functions
• Save Check Macrofunctions
• Create Default Symbols or Include Files for
  Macrofunctions
• Call Out Macrofunctions in Top-Level Design
• Remember 20/20 Rule for Future Changes or
  Additions
• Reserve 20 Logic Resources
• Reserve 20 I/O Pins

113
Altera Design Methodology
Schematic AHDL VHDL EDIF
TOP-LEVEL DESIGN
Schematic
AHDL
MACROFUNCTIONS
EDIF
AHDL
VHDL
MACROFUNCTIONS
114
Altera Design Methodology Compilation

• Select Target Device
• Set Applicable Logic Option Assignments
• Individual Macrofunction-to-Macrofunction Basis
• Global Top-level Design-wide Basis
• Compile Top-Level Design without Pin Assignments
• Functional No Routing
• Timing Place Route
• Make Pin Assignments Recompile, if Necessary
• Examine Report File (.rpt)

115
Altera Design Methodology Verification

• Simulation Verifies Whether Design Functions Are
  Correct
• Functional No Timing Information
• Timing Check for Glitches, Static Hazards, etc.
• Timing Analysis Verifies Whether Design Meets
  Performance Requirements
• Delay Matrix Combinatorial Delays
• Setup/Hold Matrix Setup/Hold Times
• Registered Performance Maximum Frequency (fMAX)
• When Satisfied with How MAXPLUS II Has Routed
  Design
• Back-Annotate Project Locks down Pin Logic
  Option Assignments

116
Design Entry MAXPLUS II
Design Entry
Library Mapping File (.LMF)
Mix Match Different Methods of Design Entry
117
Graphic Design Entry
Libraries
118
Graphic Design Entry
Graphic Design
Enter Symbol
Connect Wire
Label Wires/Pins
119
Altera Hardware Description Language

• High-Level, Hardware Behavior Description
  Language
• Uses Boolean Equations, Arithmetic Operators,
  Truth Tables, Conditional Statements, etc.
• Especially Well-Suited for Large or Complex State
  Machines
• All Described Behavior Is Implemented
  Concurrently
• Use Insert AHDL Template in the Text Editor

120
Hierarchical Design Management

• A Top-Level Design Incorporates All Lower-Level
  Elements (Macrofunctions) of the Design into a
  Single File
• Use the Hierarchy Display to Examine Navigate
  through the Design Hierarchy
• Hierarchy Display Also Shows Ancillary Files
  (e.g., Report, Simulation Input/Output, Message)

121
Hierarchical Design Management

• Use Top-down or Bottom-up Design Methodology
• Build Your Design out of Lower-Level Building
  Blocks (Called Macrofunctions)
• Create Large, Complex Designs that Are Easy to
  Manage
• Use the Library of Parameterized Modules (LPM) to
  Create Architecture-Independent Designs
• Use Specialized Altera Macrofunctions to Meet
  Your Design Goals in Specific Target Markets
  (e.g., PCI, PCMCIA, ATM, DSP)

122
Design Compilation Flow
Compilation
Timing SNF Extractor
Functional SNF Extractor
Functional
Timing
Simulation
Simulation
DifferentImplementation
Correct?
Correct?
Yes
No
No Turn on DesignDoctor
Design Entry
Yes
DifferentLogic Options
Timing Analysis
Speed?
No
Yes
Program
123
Design Compilation Compiler

• Detects Locates Errors in Design Files
• Performs Logic Synthesis/Minimization
• Performs Design Rule Checking (Design Doctor)
• Fits Design Into Target Device
• Creates Simulation Files (.snf)
• Creates Device Utilization Report (.rpt)
• Creates Device Programming Files (e.g., .pof,
  .sof)

124
Design Compilation Device Selection

• Automatic Device Selection
• MAXPLUS II Chooses the Smallest Possible Device
  from the Selected Device Family
• Select Auto as the Device in the Device Dialog
  Box (Assign Menu)
• MAXPLUS II Can Partition Your Design Into
  Multiple Devices
• Select Auto Device in the Device Dialog Box
  (Assign Menu)
• Manual Device Selection
• Select Your Targeted Device in the Device Dialog
  Box (Assign Menu)

125
Design Compilation Logic Synthesis

• Logic Synthesis Options Influence How MAXPLUS II
  Implements Your Design in the Device Architecture
• Logic Synthesis Options Set in Design Editors or
  Compiler
• Global Logic Assignments Top-level Design-wide
  Basis. Let MaxPlus II make most of the
  decisions.
• Individual Logic Assignments Macrofunction-to-Mac
  rofunction Basis. User has more control in
  guiding MaxPlus II
• Set of Predetermined Choices for Synthesis
  Options Is Called a Logic Synthesis Style
• Use the Default Synthesis Styles or Create Your
  Own
• Consult On-Line Help for a Complete Description
  of Logic Synthesis Options Styles

126
Design Compilation Compiler Menus

• Processing Menu
• Design Doctor Checks Reliability of Design
• Functional SNF Extractor Functional Compilation
• Timing SNF Extractor Timing Compilation
• Linked SNF Extractor Board Compilation
• Fitter Settings Controls Fitting of Design
• Generate AHDL TDO File Generates a Text Design
  Output File

127
Design Compilation Compiler Menus

• Interfaces Menu
• EDIF Netlist Reader Settings Sets Library
  Mapping File for an Imported EDIF File
• EDIF Netlist Writer Generates an EDIF Output
  File
• Verilog Netlist Writer Generates a Verilog
  Output File
• VHDL Netlist Reader Setting Sets the
  User-Created VHDL Library
• VHDL Netlist Writer Generates a VHDL Output File

128
Design Compilation Compiler Menus

• Assign Menu
• Device Selects Targeted Device
• Pin/Location/Chip Makes Pin Assignments
• Timing Requirements Makes Timing Assignments
• Clique Keeps Block of Function Together
• Logic Options Individual Logic Assignments
• Probe Assigns a Unique Simulation Node Name for
  Buried Logic
• Global Project Device Options Top-level
  Design-wide Programming or Configuration Options
• Global Project Timing Requirements Top-level
  Design-wide Timing Assignments
• Global Project Logic Synthesis Top-level
  Design-wide Logic Assignments
• Back-Annotate Project Writes All Assignments to
  the assignment configuration file (.acf)

129
Report File

• Lists Complete Details on Device Utilization
• Project Summary
• Device Assignments
• Device-Specific Information
• Error Summary
• Resource Usage
• Interconnect
• Device Equations

130
Floorplan Editor
Manipulating Assignments

• Graphical User Interface for Creating/Viewing
  Resource Assignments
• Pins
• Logic Cells
• Cliques
• Logic Options
• Drag-and-Drop Capability for Assigning Pins/Logic
  Cells
• Graphical View of Current Assignments as Well as
  Last Compilation
• External Chip View In-Depth Logic Array Block
  View

131
Verification Simulation

• MAXPLUS II Creates One of Two Types of Models of
  Design during Compilation
• Functional Model
• Logical Model Only, for Functional Simulation
• Generated Quickly, No Logic Synthesis or Fitting
• Timing Model
• Logical Delay Model, for Timing Simulation
• Does Not Include Nodes that Are Synthesized Away
  during Logic Synthesis
• Simulation Channel Files (.scf) or Vector Files
  (.vec) Describe Simulation Stimulus

132
Timing Simulation
Which Nodes Can Be Simulated?

• Nodes that Are Purely Combinatorial Logic Cannot
  Be Simulated
• Node May Be Transformed after Logic Synthesis
• Node May Be Removed after Logic Minimization
• Hard Nodes Can Be Simulated
• Inputs Outputs of Devices
• Inputs Outputs of Flipflops
• Inputs Outputs of LCELL Buffers
• Inputs Outputs of SOFT Buffers Not Removed by
  Logic Synthesis

133
Verification Timing Analysis

• Timing Analyzer Is a Static Timing Analyzer
• Adds Delays from Point to Point
• Three Forms of Timing Analysis (Analysis Menu)
• Delay Matrix Calculates Combinatorial Delays
• Setup/Hold Matrix Calculates Setup Hold Times
  for Device Flipflops
• Registered Performance Calculates Fastest
  Possible Clock Frequency

134
Programming a Device
Using the Programmer MPU

• Initiate Programming with the Programmer
  Modulein MAXPLUS II
• Programmer Defaults to Programming File for
  Specified Project
• Use Select Programming File (File Menu) to Select
  Another Programming File
• Perform Programming Operation with Buttons in
  Programmer
• Master Programming Unit (MPU) Stores Last Command
  (Use Start Button to Repeat)

135
Programming a Device

• BitBlaster
• Serial Port COM Port
• PC or Workstation
• Program MAX 7000S MAX 9000 Devices via the JTAG
  Interface
• Configure FLEX 8000 FLEX 10K Devices via the
  Dedicated Configuration Pins
• Configure FLEX 10K Devices via the JTAG Interface
• ByteBlaster
• Parallel Port
• PC Only
• Faster/Cheaper
• Same Programming Capabilities as BitBlaster

136
On-Line Help
MAXPLUS II

• On-line help is a comprehensive set of
  information that is always available and
  accessible
• On-line help is available for all MAXPLUS II
  menus, dialog boxes, and terminology
• Press Shift-F1 to get Help Pointer Help on
  anything you see
• Check Procedures for How to information
• For any questions, try on-line help first

137
FLEX Design Guidelines
Design Guidelines

• Never pre-assign pins
• Assign pins as late as possible and only after
  extensive simulation
• Reserve 20 of pins and cells for changes
• Design synchronously and use dedicated global
  routing resources
• Pipeline for speed
• Limit use of carry and cascade cells
• Reduce high fan-out cells and pins

138
VHDL
VHDL

• In this class, we will
• Learn basic VHDL constructs including
• VHDL basics and data types
• arithmetic operators and combinatorial circuits
• sequential circuits and state machines
• Examine VHDL synthesis for programmable logic
• Implement several VHDL designs in MAXPLUS II

139
Agenda
VHDL

• VHDL Basics and Lab
• Data Types and Lab
• Arithmetic Operators and Lab
• Sequential Logic and Lab
• State Machines and Lab (MAX 7000 vs. FLEX 8000
  synthesis)

140
What is VHDL?
VHDL

• IEEE Industry Standard hardware description
  language
• Description language for both simulation and
  synthesis
• Offshoot of Very High Speed Integrated Circuit
  (VHSIC) DOD program in early 1980s

141
VHDL Synthesis vs. other HDLs Synthesis
VHDL

• VHDL Tell me how your circuit should behave and
  I will give you hardware that does the job
• ABEL, PALASM, AHDL Tell me what hardware you
  want and I will give it to you

142
VHDL Synthesis vs. other HDLs Synthesis
VHDL

• Example of difference
• VHDL Give me a circuit whose output only
  changes when there is a low to high transition on
  a particular input. When that transition
  happens, make the output equal to the input until
  the next transition.
• Result VHDL Synthesis gives you a positive edge
  triggered flip-flop
• Others Give me a D-type flip-flop.
• Result Synthesis gives you a D-type flip-flop.
  The sense of the clock depends on the synthesis
  tool.

143
Unit 1
VHDL

• VHDL Basics
• Entity
• Architecture
• Assignments

144
Entity
VHDL

• Defines interface to outside world, i.e input and
  output pins
• Serves same function as a schematic symbol

Inputs
ENTITY example IS PORT ( a in BIT b out
BIT) END example
Outputs
145
Ports
VHDL

• Defined in ENTITY
• Ports can be IN, OUT, INOUT

146
Architecture
VHDL

• Defines implementation of design, i.e. logic
  equations
• Serves same function as a schematic

ARCHITECTURE pld OF example IS BEGIN b lt a END
pld
Logic equations go between BEGIN and END
147
Example of Complete Design
VHDL
ENTITY defines ports of design
ENTITY example IS PORT ( a in BIT b out
BIT) END example ARCHITECTURE pld OF example
IS BEGIN b lt a END pld
ENTITY and ARCHITECTURE make a pair linked by name
ARCHITECTURE defines implementation
148
PROCESS Statement
VHDL

• Groups sequential statements
• WAIT Statement or Sensitivity list describes
  conditions for executing PROCESS
• Within the process, statements are executed
  sequentially

149
PROCESS Statement
VHDL
Using the Sensitivity List
This process is executed after a change in
any signal in the Sensitivity List
150
PROCESS Statement
VHDL

• PROCESS
• BEGIN
• WAIT condition
• -- Sequential statement 1
• -- .....
• -- Sequential statement N
• END PROCESS

Using the WAIT statement
This process is executed when the WAIT
conditionis true!
151
PROCESS Statement
VHDL

• Use LABELS for organization

label PROCESS (sensitivity_list) BEGIN --
Sequential statement 1 -- ..... --
Sequential statement 2 END PROCESS label
The label identifies specific processes in a
multi-process architecture
152
Signal Assignment Examples
VHDL
q lt r or t

• Simple
• Conditional
• Selected

q lt ((r or t) and not(g xor h))
q lt 0 WHEN clr 0 ELSE 1 WHEN set
1 ELSE X
WITH sel SELECT q lt a WHEN 0 b WHEN 1
153
IF Statement
VHDL

• Chooses action based on condition
• Allows ELSIF, ELSE statements
• Must be inside PROCESS

?
154
IF Statement Example
VHDL
ENTITY if_ex IS PORT ( sel, a, b in BIT
y out BIT ) END if_ex ARCHITECTURE
if_ex OF if_ex IS BEGIN PROCESS (sel, a, b)
BEGIN IF sel '1' THEN y lt a ELSE
y lt b END IF END PROCESS END if_ex
process is sensitive to all inputs used
inside process
This circuit results in a multiplexer
155
LAB - Unit 1
VHDL

• Design 41 mux using and, or, not primitives
• Design 41 mux using IF statements
• Once the design is entered, use the Save Check
  feature (under the File-Projects menu) to check
  for syntax errors

Hint Use the VHDL Templates
156
Unit 2 - Signals and Variables, Combinatorial
Circuits, Multiple Processes
VHDL
157
VHDL Variables
VHDL
ENTITY var_ex IS PORT ( x, a, b IN BIT
z OUT BIT) END var_ex
ARCHITECTURE example OF var_ex IS BEGIN PROCESS
(x, a, b) VARIABLE tmp BIT BEGIN IF (x
'1') THEN tmp a AND b z
lt tmp ELSE z lt '1' END IF
END PROCESS END example
VARIABLE tmp holds intermediate value
158
Resulting Schematic
VHDL
159
VHDL Signals
VHDL
ENTITY sig_ex IS PORT ( a, b, c IN BIT
y OUT BIT) END sig_ex ARCHITECTURE
example OF sig_ex IS SIGNAL temp BIT
BEGIN temp lt a XOR b y lt temp AND c END
example
This SIGNAL is used to interconnect primitives
160
Resulting Schematic
VHDL
161
VHDL Signals
VHDL

• ENTITY mul IS
• PORT (a, b, c, selx, sely IN BIT
• data_out OUT BIT)
• END mul
• ARCHITECTURE ex OF mul IS
• SIGNAL temp BIT
• BEGIN
• process_a PROCESS (a, b, selx)
• BEGIN
• IF (selx 0 THEN
• temp lt a
• ELSE
• temp lt b
• END IF
• END PROCESS process_a

SIGNAL temp is used here to connect multiple
processes

• process_b PROCESS(temp, c, sely)
• BEGIN
• IF (sely 0 THEN
• data_out lt temp
• ELSE
• data_out lt c
• END IF
• END PROCESS