Lab Lectures

1
Lab Lectures

• Preparation for ECEn 320 Lab Exercises

2
Suggestions for a Productive Lab Experience

• Design
• Start early, come to lab prepared.
• Understand the assignment before you begin to
  code VHDL
• Design from your drawings-- have your block
  diagram in front of you when you write the VHDL
• Use good VHDL coding practices. Make your VHDL
  code legible.
• Comment your code.
• Simulation
• Debug using the simulator, not the board
• When you ask a TA Whats wrong with my design?
  -- be prepared to show him a simulation of the
  current design
• Save your simulation stimulus, or use do files.
  You dont have to rebuild the simulation from
  scratch every time.
• Working with the TAs
• Ask proper questions My design doesnt work.
  is not a question.
• Dont expect them to hold your hands, or read to
  you.
• Have the TAs sign your pass-off sheet when you
  have passed-off.

3
Lab 1 Seven-Segment Display Driver

• Displaying a hexadecimal number

4
Get to Know Your Spartan 3 Board
5
Spartan 3 Board
6
Lab 1 Specification
Display value on 8 switches on the seven-segment
display.Leave top two digits blank.
7
7-Segment DisplayonSpartan 3 Board
Leave Blank
8-bit Switch Value, in Hexadecimal
8
Seven-Segment Display

• Seven segment input signals (A-G) plus a
  decimal-point input signal (DP) control which
  segments are lit.
• Shared by all four digits
• Four anode control input signals control which
  digit is lit.

Board schematic of the seven-segment display
circuit
Seven-Segment Display Module
9
Seven-Segment Display

• The four anode control inputs are
  time-multiplexed (asserted at different time
  intervals, taking turns) to display data on all
  four characters.
• Present the value to be displayed on the segment
  control inputs and select the specified character
  by driving the associated anode control signal
  Low.
• Through persistence of vision, the human brain
  perceives that all four characters appear
  simultaneously, similar to the way the brain
  perceives a TV display.

10
Seven-Segment Display Timing
NoteAnode and Segment signals are all LOW
asserted.
Pattern repeats
11
Seven-Segment Decoder Logic
Note Segment signals are LOW asserted.
Switch value (4-bits)
12
FPGA Pins - Seven Segment Display
13
Switches

• When in the UP or ON position, a switch connects
  the FPGA pin to VCCO, a logic High.
• When DOWN or in the OFF position, the switch
  connects the FPGA pin to ground, a logic Low.
• The switches typically exhibit about 2 ms of
  mechanical bounce and there is no active
  debouncing circuitry, although such circuitry
  could easily be added to the FPGA design. (We
  will do this in lab 3).
• A 4.7K? series resistor provides nominal input
  protection.

14
Switches
15
Clock and Reset Circuits

• The board has a dedicated 50 MHz clock oscillator
  source.
• Use the 50 MHz clock frequency along with the
  FPGAs Digital Clock Managers (DCMs) to create
  the internal clock.
• The left-most button, BTN3, is the default User
  Reset pin.
• BTN3 electrically behaves identically to the
  other push buttons, however is used as a reset by
  convention.

16
Advantages of Using the DCM

• DCM Digital Clock Manager. (Includes the DLL).
  The Spartan 3 includes four DCMs that you can
  use.
• Filters the input clock to provide a stable
  internal clock.
• Guarantees 50 duty cycle internal clock.
• Provides a signal locked that tells when clock
  is stable and operating.
• Can be used to provide other related clocks
• A clock at twice the input clock frequency.
• Clocks at divided rates.

17
Clock and Reset Generator Circuit
FPGA Pins
clk
Internal Signals
clkfb
50 Mhz
IBUFG
(50 Mhz, 50 Duty Cycle)
clk0
clk
clk_in
clkin
clk0
clkbuf
BUFG
locked
DLL
Delay Lock Loop inDigital Clock Manager
Clkdiv(23 downto 0)
clkdiv
24-bitCounter
rst_in
Input Clock Divider
rst
set
set
set
set
(internal reset)
Reset Synchronizer
A clean clock is very important. This circuit is
the best way to generate a good clean clock in
the FPGA. Never gate the clock.
18
System Level Block Diagram
Clock Pin 50 MHz
ClockGenerator
4 MS bits
4 LS bits
clk
Multiplexer
Decoder
Clock DivideCounter
digit select
4 bits
Seven-Segment Encoder
blank
(See question 3.)
19
Lab 1 Procedure

• Design a circuit to display the 8-bit switch
  value on the two digits of the seven segment
  display.
• Use the suggested clock/reset generator circuit.
• Simulate your VHDL file with the Aldec tool.
• Synthesize your design and download your bit file
  to the board.
• Verify that your circuit works as predicted by
  simulation.
• Answer the questions.

20
Lab 1 Questions

1. The seven-segment display interface has 12 input
   pins 7 segment pins, 1 DP pin, and 4 anode pins.
   Why does the display manufacturer time-multiplex
   the display, instead of providing segment and DP
   pins for each digit ? How many pins did they
   save ? How many pins would an 8-digit display
   require if you have anode pins, and how many pins
   are needed if you dont have anode pins ?
2. The input frequency to the clock divider is 50
   MHz. Make a table of the frequencies of each of
   the 24 clock divider output bits, clkdiv(23
   downto 0) where clkdiv(0) is the LSB and
   clkdiv(23) is the MSB.
3. If you scan the digits too slow, they will appear
   to flicker. If you scan the digits too fast,
   they will be dim. What bits of the clock divider
   did you decode to drive the anodes of the
   seven-segment display ? What is the
   corresponding scanning frequency ? How did you
   decide what clock divider bits to use ?
4. When a switch is in the high position, what is
   the resistance between VCCO power and the FPGA
   input pin ? What is the resistance between
   Ground and the FPGA input pin when the switch is
   in the low position ?
5. The reset synchronizer circuit given here
   guarantees that the internal reset is on at least
   how many clock cycles ? Does the circuit
   guarantee that internal reset signal rises and
   falls synchronous to the clock ?

21
Lab 1 Objectives

• Learn to use the Aldec simulation tool.
• Learn to use the Xilinx synthesis and
  implementation tools.
• Design a working VHDL circuit.
• Learn how to properly generate a clock and reset
• Learn how to properly divide a clock
• Learn how to properly drive the seven-segment
  display.
• Learn how to download your design to the board.

22
Lab 2 UART

• Transmitting and Receiving Serial Data

23
The ABCs of Serial Ports

• UART Universal Asynchronous Receiver/Transmitter
  
• TX Transmitter
• RX Receiver
• TD Transmit Data (Data output)
• RD Receive Data (Data input)
• RTS Request to Send (Flow control output)
• CTS Clear to Send (Flow control input)
• Half Duplex transmits one direction at a time
  (mostly obsolete now)
• Full Duplex transmits both directions at the
  same time
• RTS/CTS Flow control for full duplex serial ports
  
• RX assert RTS when it is ready to receive
• TX waits for CTS before transmitting

24
Serial Port Devices

• The following is a list of various hardware
  components that use Serial Ports
• Mouse - One of the most commonly used devices for
  serial ports.
• Modem - Used commonly with older computers.
• Network - One of the original uses of the serial
  port, which allowed two computers to connect
  together and transfer large files between the
  two.
• Printer - Mostly used with older printers only.
• ASCII Terminal (TTY) - Like the Hyperterm
  interface.

25
Hooking Up Two Serial Ports
Full Duplex
TD RD RTS CTS GND
TD RD RTS CTS GND
26
Serial PortonSpartan 3 Board
DCD
DSR
RXD
RTS
TXD
CTS
DTR
RI
27
Serial Communication Format

• Data is transmitted sequentially, one bit at a
  time.
• To inform the receiver that a new byte is
  arriving, a start bit (a zero) is sent first.
  A start bit can start at any time.
• Then the data is transmitted, LSB (least
  significant bit) first, and MSB (most significant
  bit) last.
• At the end, one or two stop bits (ones) are
  transmitted.
• A frame consist of
• 1 start bit (a zero)
• 7 or 8 data bits LSB (least significant bit)
  first
• 1 optional parity bit
• 1 or 2 stop bits (ones)
• Between transmissions, the transmitter transmits
  a high.
• The bit time is determined by the baud rate which
  is given in units of BPS (bits per second).
• Transmitter and receiver do not share a clock
  (hence the asynchronous nature).

28
Serial Frame
http//www.atmel.com/dyn/resources/prod_documents/
DOC0941.PDF
http//www.wcscnet.com/Tutorials/SerialComm/Page1.
htm
29
Transmitting
30
Receiving
1.5 bit time
1.5 bit time
31
Receiver Sample Timing
Slightly Faster Baud Rate
Exact Baud Rate
Slightly Slower Baud Rate
1BitTime
1.5Bit Time
32
Lab 2, Part 1UART Transmitter
33
Lab 2, Part 1 Specification
Send ASCII value on 8 toggle switches to serial
port for display on screen when button 1 is
pressed.
34
Top Level System Block Diagram
Clock/Reset Generator Switch and Button
InterfaceButton Debouncer
Two Entities tx_test - top level file to test
the transmitter tx - The transmitter itself,
which is instantiated in the body of tx_test You
will need the transmitter (tx) for Part 3. of
this lab.
tx_test
tx Transmitter
35
Transmitter Tester (tx_test)Block Diagram
tx
clk (50 MHz) rst
Clock/Reset Generator
clk_in
Debounce Circuit
send_character
button
serial_out
tx_complete
(open, or LED)
txd
8
data_in
switch(7 downto 0)
ctsn
36
Clock and Reset Generator Circuit
FPGA Pins
clk
Internal Signals
clkfb
50 Mhz
IBUFG
(50 Mhz, 50 Duty Cycle)
clk_in
clk0
clk
clkin
clk0
clkbuf
BUFG
locked
DLL
Delay Lock Loop inDigital Clock Manager
rst
set
set
set
set
(internal reset)
Reset Synchronizer
No external reset button, rst is internally
generated.
37
Transmitter (tx) Block Diagram
clk rst
SerialGenerator
data_in
serial_out
8
stopBit
bit_sel
3
startBit
FSM
BitCounter
clk rst
send_character
clrCount
ctsn
bit7
clkrst
incCount
BitTimer
clk rst
tx_complete
tx_bit
clrTimer
38
Bit Timer - Transmitter Clocking

• Everything is clocked on same global clock (clk)
• Global clock is 50MHz
• The Bit Timer controls the timing of bits coming
  out of the serial port.
• Bit Timer needs to create timing pulse at rate of
  19,200Hz
• That is the baud rate of our serial port
• Divide factor 50,000,000/19,200 2604.1666
• We will use 2604 cycles/pulse

39
Transmitter Bit Timer

• Is a counter
• Can be cleared, otherwise increments up to 2603
  and rolls over
• Signal tx_bit is asserted when it reaches 2603

clk
tx_bit
2604 cycles
state
serial_out
one bit
40
Hints for Creating the Bit Timer
signal timer std_logic_vector(11 downto
0)signal tx_bit std_logic
process(clk)begin -- create bit timer
counter -- clrTimer and rst are synchronous
clears -- wraps to 0 after counting to 2603
(A2B hex)end process -- combinational tx_bit
lt 1 when timer XA2B else 0
2603 (decimal) A2B (hex) 101000101011 (binary)
41
Transmitter Bit Counter

• Is a counter
• cleared synchronously with clr_count
• incremented with inc_count
• counts from 0 to 7 and then wraps to 0
• It counts how many bits have been transmitted
• The count is a 3-bit bit_sel output that selects
  which data bit is to be sent next.
• bit7 tells FSM when its current count7(Means
  the last bit is being transmitted)

42
Serial Generator

• Outputs a 0 when startBit is high
• Outputs a 1 when stopBit is high
• Outputs selected data bit fromdata_in otherwise
• Output of combination logic should be registered
  using a flip-flop to ensure clean serial_out
  signal
• The Flip-Flop will remove any transient glitchs.
• IFL register design (MUX gates FF)
• Synthesizer will infer synchronous set/clear on
  FF from startBit and stopBit if possible

CombinationalLogic
43
Transmitter FSM

• FSM handshakes with outside world

send_character
tx_complete
data_in

serial_out
Data transmission here
Start bit
Stop bit
44
Transmitter FSM

• Controls start/stop bits to Serial Generator
• Controls clearing/increment of Bit Counter
• Controls clearing of Bit Timer
• Reacts to Bit Counter and Bit Timer

45
Transmitter Data Types

• All inputs/outputs should be either
• std_logic
• std_logic_vector
• Internal signals (timer and counter values)
• UNSIGNED will work
• Allows use of in code
• If needed cast port wires to/from
  std_logic_vector inside transmitter
• (You wont have to in this design)

Hidden
46
Transmitter FSM
send_character ctsn
send_character
rst
send_character
IDLE
RETRN
stopBittx_complete
send_character ctsn
stopBitclrCountclrTimer
START
tx_bit
tx_bit
startBit
tx_bit
stopBit
RUN
STOP
tx_bit
tx_bit bit7
tx_bit
tx_bit bit7 / incCount
We will give you the state machine for this lab,
for the next lab you will design your own!
47
Output Glitching

• Signal serial_out should be clean (not glitch)
• If it is register output it will be clean (in
  tx serial generator)
• Signal tx_complete should also be clean
• Run it through flip flop after it leaves FSM (in
  tx)
• Signal send_character should be clean
• Filter the push button through a button
  debouncer (in tx_test)
• What about other signals ?
• Since they drive other circuitry in the same
  clock domain dont care

48
Button Debounce Circuit
button settle time is typically around 10 msec
switch settle time
switch settle time
buttoninput
DebounceLogic
output
A digital equivalent of a low pass filter
49
Debounce Circuit
Timer/Clock Divider
clk
en_sample
Tsample gt Tsettle
D Q
en
bouncy
debounced
clk
en_sample
Tsample
bouncy
Tsettle
debounced
50
Forcing a One-Hot Encoding
type states is (IDLE, START, RUN, STOP,
RETRN) signal CS, NS states attribute
ENUM_ENCODING STRING attribute ENUM_ENCODING of
states TYPE is
00001 00010 00100 01000 10000"
Hidden

• Do this and synthesizer will
• Force this encoding
• Ensure FPGA wakes up in first state
• This will ensure that tx_complete is clean

51
Suggested Incremental Design Process

• Create file tx.vhd with all its ports and
  internal signals
• Use port names from drawing other circuitry
  expects these names
• Design Bit Timer as a process in it
• Simulate it
• Then, simulate everything else with it having
  MUCH SMALLER terminal count (how about 4 instead
  of 2604?)
• Add Bit Counter process
• Simulate everything so far
• Add Serial Generator process
• Simulate everything so far
• Add FSM processes
• Simulate entire circuit
• Dont forget to change timer terminal count back
  before synthesizing

52
Three Testing Options

• Add Aldec simulators to your inputs
• Create a simulator for each input using Add
  Simulator in Aldec
• Like you learned in the tutorial
• Write a do file
• Create a file containing simulator commands such
  as force statements using the simulators script
  language
• Run this script to run your simulation
• Dr. Nelsons favorite method
• Write a test bench
• Create a test bench entity (no inputs or outputs)
• Write VHDL in the test bench architecture to
  driveyour unit-under-test (UUT)

TestBench
UUT
VHDL
53
Lab 2, Part 1 Procedure
You Will

• Code the transmitter (tx) from the specification
  (the lab notes) and block diagram.
• Simulate the transmitter
• Build the hardware test environment (tx_test) for
  the transmitter (tx)
• Synthesize, download, and test the system
  (tx_test) on the board

54
Lab 2, Part 1 Objectives
You will learn how to . . .

• Design starting from a specification and block
  diagram
• Properly clock something at a fraction of the
  clock speed (tx_bit)
• Code a state machine, counter, and multiplexer in
  VHDL
• Instance one entity (tx) inside another (tx_test)
• Debug using simulation

55
Lab 2 Part 1 Questions

• At 19200 baud, how many characters per second can
  be transmitted? (For all questions, assume 8
  data bits, no parity, and one stop bit.)
• At 19200 baud, what is the bit time (length of
  time each bit is transmitted)?
• What percent of transmission time is overhead
  (time of the start and stop bits divided by the
  total frame time)?
• Suppose a file of 10,000 bytes is to be sent over
  a line at 19200 bps. How much time will it take?
  (In seconds)
• For the bit and timer counters, why is it
  important for the clears to be synchronous clears
  (instead of asynchronous clears)?

56
Lab 2 Part 1 Solutions
57
UART Transmitter

• You are provided
• A block diagram and state machine
• A test bench
• You have to
• Answer the questions
• Code the UART Transmitter in VHDL
• Simulate your VHDL model
• Test ( debug! )

Hidden
58
SRL16E
Hidden
59
SRL16E
DELAY-2
Hidden
Q
CE
CLK
signal shifter std_logic_vector(DELAY-1 downto
0)signal EN std_logicsignal D
std_logicsignal Q std_logic process
(clk)begin if clk'event and clk'1' then
if EN'1' then shifter lt shifter(DELAY-2
downto 0) D end if end ifend
process Q lt shifter(DELAY-1)
All fits in one LUT
60
UART Transmitter Block Diagram
clk
data_in (7-0)
01234567
clk
ready
send_character
FD
ctsn
FDRS
serial_out
sync
S R
tx_bit ready/ tx_stop
idle
ready/ tx_stop
tx_start
tx_stop
tx_run
Hidden
tx_stop
ready/ start_bit, tx_stop
clk
tx_bit ready/ start_bit, tx_stop
clk
bit_sel (2-0)
start
bit_sel7
CE
tx_bit/ tx_start
1
FDRE
7
sync
R
tx_complete
FD
tx_bit/ tx_start
bit_sel7
tx_start
(tx_bit bit_sel7)/ tx_run
run
tx_run
en_16_x_baud
tx_bit
tx_bit bit_sel7/ tx_run
en_16_x_baud
stop
clk
tx_bit/ tx_stop
start_bit
CE
CE
CE
delay 14
tx_stop
FDE
FDE
SRL16E
FDE Cclk CE en_16_x_baud
tx_bit
61
Part 2 UART Receiver
62
One Way to do a Receiver
en_16_x_baud
clk
CE
CE
CE
CE
CE
CE
CE
CE
data4
delay 15
delay 15
delay 15
delay 15
FD
FD
FDE
FDE
FDE
FDE
serial_in
(4)
(5)
(6)
(7)
stop_bit
data_out (7-0)
en_16_x_baud
Hidden
Load all the bits after the start bit into a long
shift register. Pick off the positions which
correspond to sample points
clk
start_bit
CE
CE
CE
CE
CE
CE
CE
CE
CE
CE
delay 15
delay 15
delay 15
delay 15
delay 15
data4
FDE
FDE
FDE
FDE
FDE
(0)
(1)
(2)
(3)
data_out (7-0)
purge
stop_bit
en_16_x_baud
clk
CE
CE
start_edge
CE
CE
CE
delay 6
start_bit
delay 916881716
FDE
FDE
FDE
valid_reg_delay(8)
edge_delay
valid_char
clk
valid_char
data_strobe
FD
en_16_x_baud
63
For This Lab

• Design the receiver like the transmitter
• Block Diagrams
• FSM counters
• Need to count a half-bit position to get into
  middle of bit
• You will need a shift register
• Code as shown in VHDL class lecture notes

64
Lab 2, Part 2 Specification
Keyboard character is displayed on seven segment
display when key is pressed.
65
Receiver Bit Timer

• Is a counter
• Can be cleared, otherwise increments up to 2603
  and rolls over
• Signal rx_bit is asserted when it reaches 2603
• Signal rx_half_bit is asserted when it reaches
  ???? (You choose).

clk
rx_bit
clrTimer
2604 cycles
rx_half_bit
state
serial_in
start
one bit
exactly 1.5 bit time 3906 cycles
66
Break

• A long low time on the serial_in line.
• If there is not a stop bit (high) where you
  expect one, your receiver should ignore the
  preceding byte and wait until the serial_in line
  goes high before proceeding.

ignore char
wait for high
Start bit
Stop bitexpectedhere
67
Lab 2, Part 2 Objectives
You will learn how to . . .

• Design starting from a specification and block
  diagram
• Properly clock something at a fraction of the
  clock speed (tx_bit)
• Code a state machine, counter, and multiplexer in
  VHDL
• Instance one entity (tx) inside another (tx_test)
• Debug using simulation

68
Lab 2 Part 2 Questions

• At 19200 baud (ignoring rise and fall times) how
  much variation in the baud rate can be tolerated
  by the receiver?(X , -Y )
• Why is it bad to use an output of an FSM to drive
  an asynchronous clear to a counter.
• Explain how glitches are created in combinational
  logic (such as the output forming logic of an
  FSM), and how a flip-flop can filter out these
  glitches.

69
Lab 1 Part 2 Solutions
1.
Slightly Faster Baud Rate 9.5 bit times
Exact Baud Rate 10 bit times
Slightly Slower Baud Rate 10.5 bit times
1BitTime
1.5Bit Time
70
Lab 2 Part 2 Solutions
71
UART Receiver Block Diagram
clk
serial_in
SOLUTIONHIDDENSLIDE
rd
FD
FD
data_out(7-0)
7 6 5 4 3 2 1 0
idle
rd/ rx_rst
clk
rd/ start_bit, rx_rst
CE
CE
CE
CE
FDRE
FDRE
FDRE
FDRE

sync
sync
sync
sync
start
R
rx_bit/ rx_run, rx_start
R
R
R
rx_rst
clk
bit_sel7
rx_bit/ rx_run, rx_start
clk
CE
bit_sel (2-0)
1
run
FDRE
(rx_bit bit_sel7)/ rx_run
sync
R
data_strobe
FD
rx_strobe
rx_bit bit_sel7/ rx_run
rx_run
rx_bit rd/ rx_strobe
rx_bit
stop
rx_bit
en_16_x_baud
clk
rx_bit rd
start_bit
CE
CE
CE
delay 14
FDE
FDE
CE
break(rst)
delay 8
rd
rx_run
SRL16E
rd
SRL16E
rx_start
FDE Cclk CE en_16_x_baud
72
Part 3 Full UART
73
Lab 2, Part 3 Specification
Keyboard character is displayed on screen when
key is pressed.
74
FIFO - First In First Out Buffer
bbfifo_16x8

• Store bytes (8-bit chunks) of data.
• Bytes come out in the same order that they go in.
• Can store up to 16 bytes in the buffer.
• Writing the FIFO puts a byte in the buffer.
• Reading the FIFO takes a byte out of the buffer.

75
bbfifo16x8Inputs and Outputs
tx
rx
Data_in Write Full Half_Full
Data_out Read Data_present
rxd
txd
Clk Reset
bbfifo_16x8
This FIFO stores data that has been received,but
has not yet been transmitted.
76
FIFO Inputs/Outputs

• Clk (input)
• Reset (input) An active HIGH input causes the
  16-byte internal buffer to be reset hence, all
  data currently in the buffer is lost. The
  buffers are initialized to an empty state
  following power-up. Therefore, this signal is not
  used (and is therefore tied LOW) in most cases.
• Data_in(7-0) (input) This is the data input to
  the buffer, which should be stable during an
  active WRITE clock cycle.
• Full (output) This signal becomes active HIGH
  when the 16-byte buffer is full. For the writer,
  it means that WRITE should not be applied until a
  READ creates a space in the buffer (BUFFER_FULL
  returns LOW). Any attempt to write data to a full
  buffer are simply ignored.
• Half_full (output) This signal becomes active
  HIGH when the 16-byte buffer is half full.
• Write (input) An active HIGH input indicates that
  the data currently being applied to the
  DATA_IN70 port is written to the buffer on the
  next rising clock edge. Note that write
  operations take place on every rising edge when
  this signal is active HIGH. Hence, this signal
  should be pulsed HIGH for one cycle only, unless
  new data is applied to DATA_IN70 every clock
  cycle for a burst write.Note The data is not
  stored if the BUFFER_FULL signal is active HIGH.
• Data_out(7-0) (output) This is the data output
  from the buffer. This data is valid when
  DATA_PRESENT is active HIGH, and is the current
  byte being read.
• Data_Present (output) This signal is active HIGH
  when the buffer contains one or more bytes of
  data. It also signifies that DATA_OUT70 is
  valid data.
• Read (input) An active HIGH input indicates that
  the data currently being provided at the
  DATA_OUT70 port has been read (or will be read
  on the next rising clock edge) and that the next
  available data can be made available. The READ
  input can be applied for consecutive clock cycles
  to perform a burst of data. An attempt to READ
  without DATA_PRESENT being asserted has no effect.

77
FIFO Write
DATA_PRESENT
78
FIFO Read
Single read
Burst read of 5 bytes
79
Changes to the Transmitter FSM

• FSM handshakes with outside world (revised)
• This new handshake make the transmitter easier to
  adapt to the FIFO

send_character
single cycle pulse
tx_complete
data_in

serial_out
Data transmission here
Start bit
Stop bit
80
Changes toTransmitter FSM
send_character ctsn
(RETRN Give time for send_character to go low)
rst
IDLE
RETRN
HIDDEN
stopBit
send_character ctsn
stopBitclrCountclrTimer
START
tx_bit / tx_complete
tx_bit
startBit
tx_bit
stopBit
RUN
STOP
tx_bit
tx_bit bit7
tx_bit
tx_bit bit7 / incCount
81
Lab 2, Part 3 Objectives
You will learn how to . . .

• Structurally design a higher level circuit, using
  blocks that have previously been developed.
• Be able to use an existing block developed by
  someone else, by reading a specification of its
  inputs, outputs, and timing.
• Pay attention to synthesizer warnings.

82
Lab 3The Xilinx PicoBlaze Microcontroller
83
PicoBlaze Architecture Features

• Program memory 1024 18-bit instructions
• Register file 16 8-bit general-purpose
  registers
• Flags Zero and Carry
• Scratch-pad Memory 64 8-bit locations
• Call/Return Stack 31 entries deep
• I/O port 8-bit data, 8-bit address
• Timing 2 clock cycles per instruction
• Interrupt Response 5 clock cycles

84
Microcontroller Vs. LogicCoDesign Tradeoffs
85
The PicoBlaze

• Most of the following slide images were taken
  from PicoBlaze Users Manual there is a link to
  that from Lab 3s WWW page

86
PicoBlaze Program Memory
CLK
87
I/O Interface
88
Reset
Clock
89
VHDL - Declarations
90
VHDL - Instantiations
91
Instruction Set Summary

• Bitwise Logical AND, OR, XOR, TEST
• Arithmetic ADD, SUB, COMPARE
• Shift and Rotate RL, RR, SLx, SRx, SRA
• Data Movement LOAD, FETCH, STORE, IN, OUT
• Jump and Branch JUMP, JUMP Z, JUMP NZ
• Subroutine CALL, RETURN, RETURN Z, RETURN NZ
• Interrupt ENABLE, DISABLE, RETURNI

92
Bitwise Logical Instructions
93
Arithmetic Instructions
94
Shift and Rotate Instructions
95
Shift and Rotate Instructions
96
Data Movement Instructions
(Constants)
97
Data Movement Instructions
98
Program Control Instructions
99
Jump Instructions
100
Call Instructions
101
Interrupt Control Instructions
102
Input Port
103
Input Port Decoding
MUX selects which devices signals are fed into
IN_PORT
IN_PORT70
OUT_PORT70
OUT_PORT70
Input Devices
PORT_ID70
READ_STROBE
WRITE_STROBE
READ_STROBE can be used to indicate that
something has been read
104
Use of READ_STROBE

• Some devices dont care when you read them
• Switches
• No need to even look at READ_STROBE
• Some devices do care when you read them
• FIFO
• Use READ_STROBE to indicate when a data value has
  been consumed so it can be removed

105
Faster Input Decoding
Since PORT_ID is valid for 2 cycles, can add flip
flop to reduce critical path
IN_PORT70
OUT_PORT70
OUT_PORT70
Input Devices
PORT_ID70
READ_STROBE
WRITE_STROBE
106
Output Port
107
One-Hot Decoding for a Few Registers
108
Decode Pipelining Improves Performance
(optional)
(optional)
109
Assembler
110
Assembler Directives
111
A PicoBlaze Skeleton Program
112
Lab 3 - Board Controller
113
A Two-Part Lab

• Part 1 of the lab consists of adding devices and
  doing some simple programming
• Part 2 consists of extending hardware and doing a
  complete application

114
Part 1 Description Specification

• Spartan 3 board is connected to a serial channel
  on the computer, which is running a
  hyper-terminal program.
• When a character is typed on the keyboard, it is
  echoed back to the screen
• The ASCII value of the last character typed is
  displayed on the LEDs.
• The previous two characters are displayed on the
  seven segment display.

LastChar
Echo
Next Prev PrevChar Char
115
Part 2 Description

• Spartan 3 board is connected to a serial channel
  on the computer, which is running a
  hyper-terminal program.
• The 8-bit value on the 8 toggle-switches on the
  board is displayed as 2-hex digits on the
  terminal.
• A 4-hex digit value typed on row 3 of the screen
  is also displayed on the seven-segment display on
  the board.
• This value can then be incremented, decremented,
  and cleared using push-buttons.

116
Screen Specification Part 2
117
Screen Specification
IncrementDecrementReset
Other button and LEDs are for your use (debugging)
118
Lab 3 Hardware
119
Block Diagram
(Ports)
0
FIFO
Rx
0
FIFO
Tx
1
UART Status
high
low
2 (lo)
Segment Reg
3 (hi)
4
Switch Reg
5
Button Reg
CodeBlock RAM
6
LED Reg
120
Segment Register Part 1

• Two bytes, Read/Write
• What ever is in segment register is displayed on
  seven-segment display

LED Register Part 1

• 8-bits Read/Write
• Used for debugging (you can display anything you
  want on the LEDs)
• Each bit of the register is tied to an LED

121
Switch Register - Part 2

• Need not be debounced
• 8-bits, Read only
• The switch value goes to the port multiplexer

switch_reg(to port input multiplexer)
3.3V
0V
122
Button Register Part 2

• Needs to be debounced
• 4 bits for 4 buttons, upper 4 bits are 0s
• Read/Write
• A bit is set when the button is pushed (rising
  edge of button)
• A bit is reset when a 1 is written to that bit
  (You only clear the buttons you caught-- makes
  sure no buttons are missed).

input s0, button_reg read buttonsoutput s0,
button_reg reset buttons that were caughttest
s0, 01 test bit 0 (button 1)jump
NZ, do_button1 jump if button1 was set
123
Button Register Part 2
button
Bit in button register is set when the button is
pushed (rising edge of button)
set on button push
button_reg
reset
3.3V
DebounceLogic
button_reg(to port_in multiplexer)
EdgeDetect
clk
set reset
button
0V
Sync SR
k
write_strobe
k
port_id5
Reset when a 1 is written to that bit in the
button register
port_out
124
Debounce Circuit
switch settle time is typically around 10 msec
switch settle time
switch settle time
input
DebounceLogic
output
A digital equivalent of a low pass filter
125
Debounce Circuit
Timer/Clock Divider
EdgeDetect
clk
en_sample
Tsample gt Tsettle
D Q
en
bouncy
debounced
clk
en_sample
Tsample
bouncy
Tsettle
debounced
126
Edge Detector
clk
D Q
in
rising_edge
127
Synchronous Set-Reset Flip Flop
Flip-Flop Excitation Table
Clk
Set Rst Q(t) Q(t1) 0 0 0 0 0 0 1
1 0 1 0 0 0 1 1 0 1 0 0
1 1 0 1 1 1 1 0 ? 1 1 1 ?
mem
Set
Q
D Q
Rst
rst
set
Set Override Sync SR ff
setandrst
Clk
Rst
Q
D Q
Set
Reset Override Sync SR ff
Note Use bitwise AND, OR, and NOT operators to
do SR registers
128
Lab 3 Software
129
PicoBlaze Code Hints
compare s0, s1jump Z, label
Arithmetic Comparisons Conditional Jumps, Calls,
and Returns
compare s0, s1jump NZ, label
compare s0, s1jump NC, label
compare s0, s1jump C, label
call Z, labelcall NZ, labelcall NC, labelcall
C, label
return Zreturn NZreturn NCreturn C
130
PicoBlaze Code Hints
load s0, constantoutput s0, reg1
Register Input/Output
input s0, reg1output s0, reg2
add s0, 01addcy s1, 00
Multi-byte Arithmetic
sub s0, 01subcy s1, 00
sr0 s0sr0 s0sr0 s0sr0 s0
Logical Right and Left Shifts
sl0 s0sl0 s0sl0 s0sl0 s0
131
Polling

• The processor loops and repetitively checks
  each device to see if it has a request.

Check 1
ServiceDevice 1
Check 2
ServiceDevice 2
Check 3
ServiceDevice 3
Main polling loop
132
The Board Controller Program
The current cursor col position on row 3
Global Variablesegpos
Provided for youYou need to write
Initialize
The last value read from the switches
Global Variableswitch
CheckButtons
do_buttons
Move the cursor on the screen to position row X,
column Y
gotoXY
CheckSwitches
Prints the 4-hex digit value in segHi_reg and
segLo_reg on the screen starting at row 3, col 1.
put_seg
do_switch
CheckUART
Converts a binary value to a hex character and
prints it on the screen
do_cmd
put_hex
Support Routines
Main polling loop
133
Initialization Code

• Go to Home position and clear entire screen
• Print Title
• Initialize segment position 1 (column 1)
• Print Switches
• Initialize segment register (high and low) 0000
• Print Segment Register
• Put cursor at beginning of segment value on
  screen (row 3, column 1)
• Initialize LED Register to 00

134
ANSI Terminal Commands
Command Character Sequence
Up Arrow Esc A
Down Arrow Esc B
Right Arrow Esc C
Left Arrow Esc D
Go Home Esc H
Clear Screen Esc J
Go to row, column Esc row column H
Note Windows sends three bytes of zeros
following all commands. They should be
ignored.
135
Subroutine do_button

• Read the button register
• Write back same value to button register to clear
  the buttons
• Test for button 1 (increment)
• Increment segment register
• Transmit new segment register value to terminal
  (call subroutine put_seg)
• Test for button 2 (decrement)
• Decrement segment register
• Transmit new segment register value to terminal
  (call subroutine put_seg)
• Test for button 4 (reset)
• Jump to start of program

136
Subroutine do_switch

• Read switch register
• Move cursor to row 2, column 1 (call
  subroutine gotoXY)
• Save in last switch value (internal register)
• Convert upper 4-bits to hex character and send
  to transmitter (call subroutine put_hex)
• Convert lower 4-bits to hex character and send to
  transmitter (call subroutine put_hex)
• Move cursor to row 3, column segpos (call
  subroutine gotoXY)

137
Subroutine do_cmd

• Read a character from serial port
• If character is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F,a,
  b,c,d,e, or f
• Echo character back out transmitter
• Convert character from ascii to 4-bit binary
• Insert those 4-bits into the segment register
• segpos 1, Insert into upper 4 bits of high
  byte
• segpos 2, Insert into lower 4-bits of high
  byte
• segpos 3, Insert into upper 4-bits of low
  byte
• segpos 4, Insert into lower 4-bits of low
  byte
• Move segpos to the next position. (4 wraps back
  to 1)
• If character is escape, handle arrow keys
  (optional)
• Ignore other characters

138
Subroutine put_hex

• Converts a binary value to a hex character and
  prints it on the screen.
• Convert 4-bit binary value to hexadecimal value
• Send to UART transmitter

Subroutine gotoXY

• Move the cursor on the screen to position row X,
  column Y
• Send escape to UART transmitter
• Send to UART transmitter
• Send row to UART transmitter
• Send to UART transmitter
• Send column to UART transmitter
• Send H to UART transmitter

139
Subroutine put_seg

• Prints the 4-hex digit value in (segHi_reg,
  segLo_reg) on the screen starting at row 3,
  column 1.
• Move cursor to row 3, column 1 (call
  subroutine gotoXY)
• Convert upper 4-bits of high byte of segment
  register to hex and transmit (call subroutine
  put_hex)
• Convert lower 4-bits of high byte of segment
  register to hex and transmit (call subroutine
  put_hex)
• Convert upper 4-bits of low byte of segment
  register to hex and transmit (call subroutine
  put_hex)
• Convert lower 4-bits of low byte of segment
  register to hex and transmit (call subroutine
  put_hex)
• Move cursor to row 3, column segpos (call
  subroutine gotoXY)

140
Lab 3 Procedure

• You are provided
• A specification
• Sample VHDL and code files showing how to use a
  PicoBlaze.
• PicoBlaze source VHDL files.
• You have to
• Design the registers and decoding logic in VHDL
• Write PicoBlaze code to implement the
  specification
• Simulate your VHDL model
• Test and demonstrate

141
Lab 3 Objectives

• In this lab you will learn how to
• Design using a PicoBlaze soft processor
• Interface logic to the PicoBlaze
• Program the PicoBlaze
• Make simple codesign tradeoffs

142
Lab 4 Multiplication
143
Table-Lookup Multipliers

• How big of a ROM does it take to multiply two
  n-bit numbers?

n-bit
n-bit
ROM
A block RAM in the Spartan 3 is 16-18K
bits(dependingon how youcode it)
2n-bit
144
Lookup-Table Squarers

• How big of a ROM does it take to square an n-bit
  number?

Number of locations 2nBits/location
2n-2Total ROM size 2n x (2n-2) bits
n-bit
(n-1)-bit
lsb
n bits
ROM
ImprovedROM
A block RAM in the Spartan 3 is 16-18K
bits(dependingon how youcode it)
2n-2 bits
2n-bit
(2n-2)-bit
0
lsb
Why 2n-2 output bits in improved ROM?
145
Multiplying by Squaring
x
y
n-bit
n-bit

-
n-bit
lsb
n-bit
lsb
(n1) bits
(n1)-bits
ROM
ROM
(2n) bits
(2n) bits
2n-bit
0
lsb
2n-bit
0
lsb
-
64 Block RAMS vs.2 Block RAM 3 Adders
2n-bit
xy
146
8-Bit x 8-Bit Multiply
x
y
8-bitsigned
8-bitsigned
In your application, you will be multiplying two
8-bit signed numbers to get a 16-bit signed
result.

-
9-bitsigned
9-bitsigned
9-bits
9-bits
ROM
ROM
16-bits
16-bits
16-bitpositive
16-bitpositive
-
xy
16-bit Signed
147
Squaring ROM

• Write code which will be inferred as a ROM
  (BlockRAM)
• Input (address) is 9 bits wide
• Output is 16 bits wide
• Uses just half of the BlockRAM
• It is big enough that writing a C or Java program
  to generate design is a good idea
• Must handle signed inputs
• Same ROM is structurally placed twice in
  multiply.vhd file
• Surrounding logic interfaces it to rest of system
• Multiply two 8-bit values, return 16-bit result

148
Squaring ROM
A A2 A2/4 ROM addr (A) ROM Output
(A2/4) 0 0 0 0 0000 0000 0000
0000 0000 0000 1 1 0 0 0000 0001
0000 0000 0000 0000 2 4 1 0 0000
0010 0000 0000 0000 0001 3 9 2 0
0000 0011 0000 0000 0000 0010 4 16 4
0 0000 0100 0000 0000 0000 0100 ...
... ... 254 64516 16129
0 1111 1110 0011 1111 0000 0001 255 65025
16256 0 1111 1111 0011 1111 1000 0000-256
65536 16384 1 0000 0000 0100 0000 0000
0000-255 65025 16256 1 0000 0001 0011 1111
1000 0000-254 64516 16129 1 0000 0010 0011
1111 0000 0001 ... ...
... -4 16 4 1 1111 1100 0000
0000 0000 0100 -3 9 2 1 1111 1101
0000 0000 0000 0010 -2 4 1 1 1111
1110 0000 0000 0000 0001 -1 1 0 1
1111 1111 0000 0000 0000 0000
9-bits
16-bits
149
Squaring ROM
This ROM is large enough that a small C-program
(or any other language) would probably be useful
to generate the ROM contents. Output is on next
page. You can use or modify this program to fit
your needs.
include ltstdio.hgt main() int i for
(i0 ilt256 i) printf("04x ",
((ii)/4)0xffff) if (i1615)
printf("\n") for (i-256 ilt0 i)
printf("04x ", ((ii)/4)0xffff)
if (i16-1) printf("\n") return
0
150
0000 0000 0001 0002 0004 0006 0009 000c 0010 0014
0019 001e 0024 002a 0031 0038 0040 0048 0051 005a
0064 006e 0079 0084 0090 009c 00a9 00b6 00c4 00d2
00e1 00f0 0100 0110 0121 0132 0144 0156 0169 017c
0190 01a4 01b9 01ce 01e4 01fa 0211 0228 0240 0258
0271 028a 02a4 02be 02d9 02f4 0310 032c 0349 0366
0384 03a2 03c1 03e0 0400 0420 0441 0462 0484 04a6
04c9 04ec 0510 0534 0559 057e 05a4 05ca 05f1
0618 0640 0668 0691 06ba 06e4 070e 0739 0764 0790
07bc 07e9 0816 0844 0872 08a1 08d0 0900 0930 0961
0992 09c4 09f6 0a29 0a5c 0a90 0ac4 0af9 0b2e 0b64
0b9a 0bd1 0c08 0c40 0c78 0cb1 0cea 0d24 0d5e 0d99
0dd4 0e10 0e4c 0e89 0ec6 0f04 0f42 0f81 0fc0 1000
1040 1081 10c2 1104 1146 1189 11cc 1210 1254 1299
12de 1324 136a 13b1 13f8 1440 1488 14d1 151a 1564
15ae 15f9 1644 1690 16dc 1729 1776 17c4 1812 1861
18b0 1900 1950 19a1 19f2 1a44 1a96 1ae9 1b3c 1b90
1be4 1c39 1c8e 1ce4 1d3a 1d91 1de8 1e40 1e98 1ef1
1f4a 1fa4 1ffe 2059 20b4 2110 216c 21c9 2226 2284
22e2 2341 23a0 2400 2460 24c1 2522 2584 25e6 2649
26ac 2710 2774 27d9 283e 28a4 290a 2971 29d8 2a40
2aa8 2b11 2b7a 2be4 2c4e 2cb9 2d24 2d90 2dfc 2e69
2ed6 2f44 2fb2 3021 3090 3100 3170 31e1 3252 32c4
3336 33a9 341c 3490 3504 3579 35ee 3664 36da 3751
37c8 3840 38b8 3931 39aa 3a24 3a9e 3b19 3b94 3c10
3c8c 3d09 3d86 3e04 3e82 3f01 3f80 4000 3f80 3f01
3e82 3e04 3d86 3d09 3c8c 3c10 3b94 3b19 3a9e 3a24
39aa 3931 38b8 3840 37c8 3751 36da 3664 35ee 3579
3504 3490 341c 33a9 3336 32c4 3252 31e1 3170 3100
3090 3021 2fb2 2f44 2ed6 2e69 2dfc 2d90 2d24 2cb9
2c4e 2be4 2b7a 2b11 2aa8 2a40 29d8 2971 290a 28a4
283e 27d9 2774 2710 26ac 2649 25e6 2584 2522 24c1
2460 2400 23a0 2341 22e2 2284 2226 21c9 216c 2110
20b4 2059 1ffe 1fa4 1f4a 1ef1 1e98 1e40 1de8 1d91
1d3a 1ce4 1c8e 1c39 1be4 1b90 1b3c 1ae9 1a96 1a44
19f2 19a1 1950 1900 18b0 1861 1812 17c4 1776 1729
16dc 1690 1644 15f9 15ae 1564 151a 14d1 1488 1440
13f8 13b1 136a 1324 12de 1299 1254 1210 11cc 1189
1146 1104 10c2 1081 1040 1000 0fc0 0f81 0f42 0f04
0ec6 0e89 0e4c 0e10 0dd4 0d99 0d5e 0d24 0cea 0cb1
0c78 0c40 0c08 0bd1 0b9a 0b64 0b2e 0af9 0ac4 0a90
0a5c 0a29 09f6 09c4 0992 0961 0930 0900 08d0 08a1
0872 0844 0816 07e9 07bc 0790 0764 0739 070e 06e4
06ba 0691 0668 0640 0618 05f1 05ca 05a4 057e 0559
0534 0510 04ec 04c9 04a6 0484 0462 0441 0420 0400
03e0 03c1 03a2 0384 0366 0349 032c 0310 02f4 02d9
02be 02a4 028a 0271 0258 0240 0228 0211 01fa 01e4
01ce 01b9 01a4 0190 017c 0169 0156 0144 0132 0121
0110 0100 00f0 00e1 00d2 00c4 00b6 00a9 009c 0090
0084 0079 006e 0064 005a 0051 0048 0040 0038 0031
002a 0024 001e 0019 0014 0010 000c 0009 0006 0004
0002 0001 0000
151
(No Transcript)
152
Multiplier.vhd
Start
Done
Multiplier Timing
Load
ROM Multiplier
8-bit
8-bit
16-bit
8-bit
8-bit
153
Block Diagram
154
Lab 4 Procedure

• You are provided
• A specification
• PicoBlaze code to help you simulate your
  multiplier.
• Final PicoBlaze code to test your multiplier (you
  should not have to modify the code... unless you
  want to).
• You have to
• Design a ROM-based multiplier (signed 8-bit x
  8-bit 16-bit).
• Interface your multiplier to the PicoBlaze.
• Simulate your design
• Synthesize, download, and test

155
Lab 5 - Real Time Clock Interface
156
Specification
In this lab, you will build an alarm clock. The
things your clock should able to perform are 1
Continuously display the current time. 2 Set the
time on the clock 3 Set the alarm time on the
clock 4 Set a non-volatile value (the clock chip
has non- volatile memory on it). 5 Get the
non-volatile value from off the chip. 6 When
the alarm goes off, something interesting
should happen. You should be able to turn off
the alarm.
157
Objectives

• We will be using aDallas SemiconductorDS1687-3R
  eal Time Clock (RTC) chip.
• The objectives of the lab are to learn how to
• Interface an FPGA to an external chip
• Read data sheets
• Design your own user interface
• Handle interrupts

158
(No Transcript)
159
The Real-Time Clock Interface
RTC
8
AD
ALE
RD
WR
CS
IRQ
Time-multiplexed Address/Data
Interface to RTC by reading and writinginternal
registers
160
Address/Data Time-Multiplexing
Multiplexed buses save pins because address
information and data information time-share the
same signal paths. The addresses are present
during the first portion of the bus cycle and the
same pins and signal paths are used for data in
the second portion of the cycle.
161
RTC Pins
162
RTC Pins
163
RTC Pins
164
Unused RTC Input Pins
165
RTC Read Cycle Timing
Address
Read data
166
RTC Write Cycle Timing
Write data
Address
167
We are using the DS1687-3 Part
168
(No Transcript)
169
(No Transcript)
170
Reading/Writing Time

• The time and calendar information is obtained by
  reading the appropriate register bytes shown in
  Table 1. The time, calendar, and alarm bytes are
  always accessible because they are double
  buffered.
• The time, calendar, and alarm are set or
  initialized by writing the appropriate register
  bytes.
• The contents of the time, calendar, and alarm
  registers can be either binary or binary coded
  decimal (BCD) format. The data format (binary or
  BCD) should be set by the data mode bit (DM) of
  Register B. All time, calendar, and alarm
  registers must use the same data mode. The data
  mode cannot be changed without reinitializing the
  10 data bytes.

171
The Update ProblemAn Example

1. The current time is 55959
2. You read the hours byte 05
3. An update cycle occurs, and time changes to
   60000
4. You read the minutes byte 00
5. You read the seconds byte 00
6. You report the time as 50000 when the time is
   actually 60000.
7. The time is wrong by an hour, something bad
   happens, and you get fired.

If a read or write of the time and calendar data
occurs during an update, a problem exists where
seconds, minutes, hours, etc., might not
correlate.
172
Solution to the Update Problem
Before reading or writing the internal time,
calendar, and alarm registers, the SET bit in
Register B should be written to a logic 1 to
prevent updates from occurring while access is
being attempted. The set bit should be cleared
after reading or writing to allow the RTC to
update the time and calendar bytes. Register B
SET When the SET bit is a 0, the update
transfer functions normally by advancing the
counts once per second. When the SET bit is
written to a 1, any update transfer is inhibited
and the program can initialize the time and
calendar bytes without an update occurring in the
midst of initializing. Read cycles can be
executed in a similar manner. The RTC executes an
update cycle once per second regardless of the
SET bit in Register B. When the SET bit in
Register B is set to 1, the user copy of the
double-buffered time, calendar, alarm, and
elapsed time byte is frozen and does not update
as the time increments. However, the time
countdown chain continues to update the internal
copy of the buffer. This feature allows the time
to maintain accuracy independent of reading or
writing the time, calendar, and alarm buffers and
also guarantees that time and calendar
information is consistent.
173
Another Solution to the Update Problem
Another method exists for accessing the RTC
registers that avoids any possibility of
accessing inconsistent time and calendar data. It
uses the UIP bit in Register A to determine if
the update cycle is in progress. The UIP bit
pulses once per second. After the UIP bit goes
high, the update transfer occurs 244µs later. If
a low is read on the UIP bit, the user has at
least 244µs before the time/calendar data is
changed. Therefore, the user should avoid
routines that would cause the time needed to read
valid time/calendar data to exceed 244µs.
244µs
Register A UIP bit
1,000,000 µs 1 sec
update
update
update
update
174
The UIP Bit and the Set Bit
175
Update/Alarm Notification

• The RTC can be configured to send out a
  notification or interrupt when specific events
  occur within the chip.
• The events which can cause a notification are
  selected by configuring the control registers
• Notification is sent by the RTC pulling the IRQN
  signal to 0.
• This signal should be ties (through an inverter)
  to the interrupt pin of the PicoBlaze.
• When asserted (and if interrupts are enabled in
  the PicoBlaze), it will cause the PicoBlaze to
  interrupt, and branch to the interrupt service
  routine (ISR).
• The IRQN signal is turned off by the ISR clearing
  the appropriate flags within the RTC chip.

176
Bank
ReadOnly
0/1
1
0
0
0
0
0
RTCIRQNControl
0/1
0/1
0/1
0/1
1
0
1
0
AlarmFlag
UpdateFlag
Read Only
The Update Flag is set after time is updated. The
Alarm Flag is set when the alarm time is
reached. Both are enabled (AEI, UIE) to cause an
interrupt.
Read Only
0
0
0
0
Read Only
0
0
0
0
0
0
0
0
177
A,B,C,D REGS
178
PicoBlaze Interface
Control Register
ALE
RD
WR
EN_A
EN_D
IRQ
RTC
Interrupt
Port_InPort_Out
AD
Data
CS
CodeBlock RAM
Address
gnd
179
Interface Idea 2 -- NOT USED
start
State Machine
HIDDEN
ALE
RD
WR
EN.A
EN.D
IRQ
RTC
AD
Data
CS
CodeBlock RAM
Address
gnd
180
Driving the AD Multiplexed Bus
-- in entity declaration -- rtc pins ad
inout std_logic_vector(7 downto 0) ale
out std_logic wrn out std_logic
rdn out std_logic csn out
std_logic irqn in std_logic -- in
architecture -- PicoBlaze Interrupt interrupt
lt not irqn -- rtc interrupt -- addr is the
address register port -- data is the data
register port -- drive tri-state outputs for ad
bus ad lt addr when en_addr'1' else
data when en_data'1' else
"ZZZZZZZZ" -- ad feeds directly into mux
driving port_in
181
Input Port Timing
182
Output Port Timing
183
Real-Time Clock Interface (50 MHz)
Read Cycle Worksheet
20 ns
1.
2.
3.
4.
5.
7.
8.
6.
9.
Instruction
Port_id
1.
2.
3.
4.
5.
7.
8.
6.
9.
Strobe
Port_in
Port_out
AD
ALE
RD
WR
184
Real-Time Clock Interface (50 MHz)
Write Cycle Worksheet
20 ns
1.
2.
3.
4.
5.
7.
8.
6.
9.
Instruction
Port_id
1.
2.
3.
4.
5.
7.
8.
6.
9.
Strobe
Port_in
Port_out
AD
ALE
RD
WR
185
PicoBlaze Procedural Interface
------------------------------------
Write_RTC (write to an RTC chip register)
Parameters s0 the byte value to be
written s1 the RTC register number to write
Note Also document what other registers are
destroyed ------------------------------------
------------------------------------
Read_RTC (read from an RTC chip register)
Parameters s0 returns the byte value that
was read s1 the RTC register number to read
Note Also document what other registers are
destroyed ------------------------------------
186
Chip Pinout
3V
float
float
float
float
3V
187
RT