FPGA??????

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FPGA??????
2007?Xilinx ?????????

??13820779613 wangweibit_at_163.com
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• ????????????????????????,??????????,?????????
• ???????????
• FPGA??????????????,???????????????????,???????????
  ??
• ?????????????????????????????
• ??FPGA?????????
• FPGA???????????????FPGA????????,????FPGA????????,?
  ???????????
• ?????????I/O??????????????????

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• ??(PERIOD)?????????????????,??flip-flop?latch?syn
  chronous RAM??
• ????????????
• ????????????????????
• ???????????????
• ?????????????

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????

• ????????????????,?????????,???????????????????????
  (??????????????)????????????????(???PAD???????)?
• ?????????????????,????????????????????,???????????
  ?,??????FPGA/ASIC?????????????????????????????????
  ???,????????,??????????
• ?????????,?????????????????,??????????,???????,???
  ?,???????????,???????

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????

• ???????
• ?????????????????????????????????,????????????????
  ?
• ????????
• Tperiod Tcko Tlogic Tnet
  Tsetup-Tclk_skew
• Tclk_skew Tcd1-Tcd2
• ??Tcko???????,Tlogic??????????????,Tnet?????,Tsetu
  p??????????,Tclk_skew????????

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• ???????????
• NET SYS_CLK PERIOD10ns HIGH 4ns
• ?????????SYS_CLK????????????
• PERIOD?????????????????,??????????????,???????????
  ?????PERIOD???????

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• ???????????????,??????????????????????????
  ?,????PAD?????,?????????

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• ????????????
• ??????????????(OFFSET IN)
• ??????????????(OFFSET OUT)
• ??????????????????????????,???????????????????????
  ????????????,??????????????????????????????????,??
  ???????

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• OFFSET_IN_BEFORE
• ??????????????????????,??????????????????????????(
  ??,???),??????????
• OFFSET_IN_AFTER
• ???????????????????????????,???????????????

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????

• ????????????
• OFFSET_IN_AFTER???????????????????Tarrival??????
• TarrivalTckoToutputTlogic   
• ???????????????Tinput ??????
• Tarrival TinputTsetupltTperiod
• ??Tinput?????????????PAD?????,Tsetup????????????,
  Tcko????????????

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• ????Tperiod20ns,Tcko1ns,Toutput3ns,Tlogic8ns,
  ????????

• TarrivalTckoToutputTlogic12ns,
• ??OFFSET_IN_AFTER???????
• NET DATA_IN OFFSETIN 12ns AFTER CLK
  
• ?????OFFSET_IN_BEFORE??????,??????
• NET DATA_IN OFFSETIN 8ns BEFORE CLK

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????

• OFFSET_OUT_BEFORE
• ??????????????????????????????
• ??????????????????????????????????,???????????????
  ??????,?????????????,????????????
• OFFSET_OUT_AFTER
• ???????????????????(??,???)????,?????????????????

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• ???????????
• ??Tstable TlogicTinput Tsetup
• ????????????????????Tstable??????,?????????????
• ?????????????????????
• Tcko ToutputTstableltTperiod
• ??????Tstable????????????,??????????????????,?????
  ?????????

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• ??
• ??????20ns,????????Tinput?4ns?????Tsetup?1ns,?
  ???Tlogic????8ns,?????????????
• ??
• OFFSET_OUT_BEFORE ?????
• NET DATA_OUT OFFSETOUT 13ns  BEFORE CLK
• OFFSET_OUT_AFTER??
• NET DATA_OUT FFSETOUT  7ns  AFTER CLK

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• Given the system diagram below, what values would
  you put in the Constraints Editor so that the
  system will run at 100 MHz?(Assume no clock skew
  between devices)

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Path-Specific Timing Constraints

• Using global timing constraints (PERIOD, OFFSET,
  and PAD-TO-PAD) will constrain your entire design
• Using only global constraints often leads to
  over-constrained designs
• Constraints are too tight
• Increases compile time and can prevent timing
  objectives from being met
• Review performance estimates provided by your
  synthesis tool or the Post-Map Static Timing
  Report
• Path-specific constraints override the global
  constraints on specified paths
• This allows you to loosen the timing requirements
  on specific paths

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Path-Specific Timing Constraints

• Areas of your design that can benefit from
  path-specific constraints
• Multi-cycle paths
• Paths that cross between clock domains
• Bidirectional buses
• I/O timing
• Path-specific timing constraints should be used
  to define your performance objectives and should
  not be indiscriminately placed

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Path-Specific Timing Constraints
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Path-Specific Timing Constraints
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Path-Specific Timing Constraints
??????
??????32???????,?????????????????????
??,??????????????????,??????????????????????,?????
??????????,?????30?,?????????????????E
N?????????,?????4?CLK????,?EN??????CLK???,????????
??????1? ??,????????????CLK??1?,??????
???????1?CLK????????????,????????????1?CLK????????
?????4????????????,???????????4?CLK??????????????,
????????????4?CLK,?????????????,???????????????
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Path-Specific Timing Constraints
????
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Path-pin offset Timing Constraints

• Use the Pad to Setup and Clock to Pad columns to
  specify OFFSETs for all I/O paths on each clock
  domain. Easiest way to constrain most I/O paths
• However, this can lead to an over-constrained
  design
• Use the Pad to Setup and Clock to Pad columns to
  specify OFFSETs for each I/O pin

• Use this type of constraint when only a few I/O
  pins need different timing

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False paths Constraints

• If a PERIOD constraint were placed on this
  design, what delay paths would be constrained?
• If the goal is to optimize the input and output
  times without constraining the paths between
  registers, what constraints are needed?
• Assume that a global PERIOD constraint is already
  defined

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Timing Constraint Priority

• False paths
• Must be allowed to override any timing constraint
• FROM THRU TO
• FROM TO
• Pin-specific OFFSETs
• Group OFFSETs
• Groups of pads or registers
• Global PERIOD and OFFSETs
• Lowest priority constraints

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• ?????,????????????
• ??????????---?????????????
• ??????????---????????????
• ??????????---?????????????? ?????

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??????

• ?????????????
• ???????????????????????,????
• ????????, ?????????
• ???? Map Report ?? Place Route Report

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??????

• Project Navigator ????????
• Post-Map Static Timing Report
• Post-Place Route Static Timing Report
• ??????????????????????,????????????????????
• Timing Analyzer????????????

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??????

• ??????????
• Post-Map Static Timing Report
• ??????????(block delays)?0.1 ns????( net delays)
• ????????????60/40 ??
• If less than 60 percent of the timing budget is
  used for logic delays, the Place Route tools
  should be able to meet the constraint easily.
• Between 60 to 80 percent, the software run time
  will increase.
• Greater than 80 percent, the tools may have
  trouble meeting your goals.

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• ????????
• 1. ???????(??)??
• DSP48, PowerPC processor, EMAC, MGT,
• FIFO, block RAM, ISERDES, and OSERDES, ???
• 2. ?????????
• Use synchronous design methodology
• Ensure the code is written optimally for critical
  paths
• Pipeline( Xilinx FPGAs have abundant Registers )
• 3. ????synthesis???Place Route??????
• Try different optimization techniques
• Add critical timing constraints in synthesis
• Preserve hierarchy
• Apply full and correct constraints
• Use High effort

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Use embedded blocks
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Simple Coding Steps Yield 3x Performance
??????

• Use pipeline stages-more bandwidth
• Use synchronous reset-better system control
• Use Finite State Machine optimizations
• Use inferable resources
• Multiplexer
• Shift Register LUT (SRL)
• Block RAM, LUT RAM
• Cascade DSP
• Avoid high-level constructs (loops, for example)
  in code
• Many synthesis tool produce slow implementations

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Synthesis guidelines
??????

• Use timing constraints
• Define tight but realistic individual clock
  constraints
• Put unrelated clocks into different clock groups
• Use proper options and attributes
• Turn off resource sharing
• Move flip-flops from IOBs closer to logic
• Turn on FSM optimization
• Use the retiming option

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Impact of Constraints
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Place Route Guidelines
??????

• Timing constraints
• Use tight, realistic constraints
• Recommended options
• High-effort Place Route
• By default, effort is set to Standard
• Timing-driven MAP
• Multi-Pass Place Route (MPPR)
• Tools to help meet timing
• Floorplanning(Use the PACE and PlanAhead software
  tools)
• Physical synthesis tools
• Other available options
• Incremental design
• Modular design flows

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Impact of Constraints in Tools
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• ??Xilinx-Specific??
• ??Xilinx????
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• ??ISE???????????,????????,?????

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????

• ?????????????,???constraint-driven??,????????,????
  ??

• ???????????,???????? ????,????????,????????

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????

• ????????????,???????????????

• Register Duplication
• Timing-Driven Synthesis
• Timing Constraint Editor
• FSM Extraction
• Retiming
• Hierarchy Management
• Schematic Viewer
• Error Navigation
• Cross-Probing
• Physical Optimization

??F1???? ? XST Userguide
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Duplicating Flip-Flops
????

• High-fanout nets can be slow and hard to route
• Duplicating flip-flops can fix both problems
• Reduced fanout shortens net delays
• Each flip-flop can fanout to a different physical
  region of the chip to reduce routing congestion
• Design trade-offs
• Gain routability and performance
• Increase design area
• Increase fanout of other nets

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Timing-Driven Synthesis
????

• Synplify, Precision, and XST software
• Timing-driven synthesis uses performance
  objectives to drive the optimization of the
  design
• Based on your performance objectives, the tools
  will try several algorithms to attempt to meet
  performance while keeping the amount of resources
  in mind
• Performance objectives are provided to the
  synthesis tool via timing constraints

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????
Timing-Driven Synthesis

• ??period???input/output??(.xcf??)
• ??,???????????1.5X-2X????,???????????,????????????
  ????
• ?????????,??????????????
• ??Multi-cycle?false paths??
• ??Critical path??,?Critical path????

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Retiming
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• Synplify, Precision, and XST software
• Retiming The synthesis tool automatically tries
  to move register stages to balance combinatorial
  delay on each side of the registers

Before Retiming
After Retiming
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Hierarchy Management
????

• Synplify, Precision, and XST software
• The basic settings are
• Flatten the design Allows total combinatorial
  optimization across all boundaries
• Maintain hierarchy Preserves hierarchy without
  allowing optimization of combinatorial logic
  across boundaries
• If you have followed the synchronous design
  guidelines, use the setting
• -maintain hierarchy
• If you have not followed the synchronous design
  guidelines, use the setting -flatten the design
• Your synthesis tool may have additional settings
• Refer to your synthesis documentation for details
  on these settings

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Hierarchy Preservation Benefits
????

• Easily locate problems in the code based on the
  hierarchical instance names contained within
  static timing analysis reports
• Enables floorplanning and incremental design flow
• The primary advantage of flattening is to
  optimize combinatorial logic across hierarchical
  boundaries
• If the outputs of leaf-level blocks are
  registered, there is no need to flatten

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• ???????????????I/O?????,Xilinx??????????
• ???????????????,????????????
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• ????????????????Xilinx?????????,????I/O
  bank?I/O?????
• ??(?????)???????????
• ???????????
• ????dual-purpose??(????DCI??)

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???????????
????

• ???????I/O??????????
• ????????
• ???????I/O??????????
• ????????

• ????????????Xilinx?????????
• ???????
• ?RAM,?????

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??PACE??????
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• ?????????????,?????
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• ??multi-cycle,false path???????,?????????????????

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??????

• Post-mapMap?,??Post-map timing report???????????
• Post-PARPAR?,??Post-PAR static timing
  report??????????
• Logic delay Vs. Routing delay60/40??
• Timing Analyzer????????,??????,??Floorplanner?????
  ???

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Report Example
??????
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Analyzing Post-Place Route Timing
??????

• There are many factors that contribute to timing
  errors, including
• Neglecting synchronous design rules or using
  incorrect HDL coding style
• Poor synthesis results (too many logic levels in
  the path)
• Inaccurate or incomplete timing constraints
• Poor logic mapping or placement
• Each root cause has a different solution
• Rewrite HDL code
• Add timing constraints
• Resynthesize or re-implement with different
  software options
• Correct interpretation of timing reports can
  reveal the most likely cause
• Therefore, the most likely solution

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Case1
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Poor Placement Solutions
??????

• Increase Placement effort level (or Overall
  effort level)
• Timing-driven packing, if the placement is caused
  by packing unrelated logic together
• Cross-probe to the Floorplanner to see what has
  been packed together
• This option is covered in the .Advanced
  Implementation Options. module
• PAR extra effort or MPPR options
• Covered in the .Advanced Implementation Options.
  module
• Floorplanning or Relative Location Constraints
  (RLOCs) if you have the skill

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??????
Case2
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High Fanout Solutions
??????

• Most likely solution is to duplicate the source
  of the high-fanout net
• the net is the output of a flip-flop, the
  solution is to duplicate the flip-flop
• Use manual duplication (recommended) or synthesis
  options
• If the net is driven by combinatorial logic,
  locating the source of the net in the HDL code
  may be more difficult
• Use synthesis options to duplicate the source

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Case3
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Too Many Logic Levels Solutions
??????

• The implementation tools cannot do much to
  improve performance
• The netlist must be altered to reduce the amount
  of logic between flip-flops
• Possible solutions
• Check whether the path is a multicycle path
• If yes, add a multicycle path constraint
• Use the retiming option during synthesis to
  distribute logic more evenly between flip-flops
• Confirm that good coding techniques were used to
  build this logic (no nested if or case
  statements)
• Add a pipeline stage

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RR????Effort Level
????

• ???????Effort Level????????,?????????(???????????
  ,?????????????)
• Xilinx????????,?????????????????????????????
• ??????,??????????,??????
• ????????,?Optimization Effort ,Use Synthesis
  Constraints File ,Keep Hierarchy ,Register
  Duplication,Register Balancing ?
• ??PAR Effort Level
• Apply path-specific timing constraints for
  synthesis and implementation

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????

• ?PAR??,????Map-timing??????????????????
  Timing-Driven Packing and Placement
  ??????????????????????Translate???User
  Constraints File (UCF ) ??????? ?

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Timing-Driven Packing
????

• Timing constraints are used to optimize which
  pieces of logic are packed into each slice
• Normal (standard) packing is performed
• PAR is run through the placement phase
• Timing analysis analyzes the amount of slack in
  constrained paths
• If necessary, packing changes are made to allow
  better placement
• The output of MAP contains both mapping and
  placement information
• The Post-Map Static Timing Report contains more
  realistic net delays
• Place Route runtime is reduced because some
  placement is already done

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Example
????

• Originally, the flip-flops were packed together
  into a slice.
• After placement and timing analysis, the
  flip-flops are packed into different slices to
  allow independent movement

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Trade-Offs
????

• Typical performance improvement Five to eight
  percent
• Density improvements are also seen
• Has the greatest effect on high-density designs
  when unrelated packing has occurred
• Look in the Map Report, Design Summary section
• Number of slices containing unrelated logic
• If no unrelated packing has occurred, performance
  improvement will be minimal
• Runtime for the MAP process always increases
• Up to 200 percent
• But you recover some of this increased runtime
  by saving runtime during Place Route

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MPPR?PAR Extra Effort
????

• MPPR????????PAR??,????????????????,????????

• ??????PAR Effort Level????,PAR Extra
  Effort??????None,Normal?Continue on impossible
• ?????,??????4???
• ??PAR???????(??200??)

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Floorplanning?PACE

• ??Floorplanning?PACE??????
• ??????!!!
• ???????,?????????,??MPPR
• Map-timing?Floorplanning??????

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Floorplanning?PACE

• ???????????????,????????,??
• ????????
• ????Xilinx????
• ????Xilinx???????
• ??Floorplanner???(???????????)
• ??????,Floorplanner????????????????
• ???????????,??????
• ?incremental design???modular?????????Floorplanner

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????(Area Constraints)
Floorplanning?PACE

• Area Constraints?Floorplanner??????????
• ??????????- Floorplanner
• ????,???????component?????,??Keep Hierarchy????
• ??????????????????????
• ???????????Planahead

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