FPGA Design Software

1
Part III

• FPGA Design Software

2
Introduction
1984 (Espresso)
Two-level synthesis
Technology development
Multi-level synthesis
PLA (1980)
Symbolic minimization
Functional Decomposition (1995)
3
Basic Structures of programmable devices
4
Simple Computer Aided Design System
Project specification
Verification and Programming
compilation
Graphic Editor
Simulator
Timing Editor
Text Editor
Programmer
Timing Analyzer
Synteza logiczna i odwzorowanie technologiczne
Logic Synthesis and Technology Mapping
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PLA/PLD Logic Optimization
Reduction
( CLBs)
Silicon Area
7a
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PLA
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ESPRESSO
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PLA Silicon area
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Example adder realisation
Two-input decoder
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Types of PLA structures
AND-OR with one-bit decoder
AND-EXOR with one-bit decoder
AND-OR with two-bit decoder
AND-EXOR with two-bit decoder
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PLA with two-bit decoder
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Two Level PLA(Ciesielski)
Symbolic Minimization
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Symbolic minimization
Decoder
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Symbolic Minimization
Encoded Table Table after Espresso Minimization
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Two bit adder
Inputs/outputs
Notation in the truth table
Adder
Next page cont
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Symbolic Minimization
Two-bit adder
Positional Notation a c e 0 0 0 (first) 0
0 ? 1 0 0 0 1 0 0 0 1 0 0 (fifth)
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Adder Realization using symbolic minimization
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Two-bit adder Realization
Area reduction
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Sequential Circuits based on PLA/PLD
Multi-valued minimization
State Encoding
PLA with minimal area
symbolic minimization Minimization of the
number of States of encoding
21a
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FLEX 10K with Embedded Array Blocks
ROM
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ROM-based FSM Synthesis
X
x
q
X
b
q
x
Address modifier
a
Register
c lt b
(x q)
Register
(a c) lt (x q)
ROM
ROM
y
F
Q
y
F
Q
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FPGA based Logic Synthesis
CLBs
channels
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Logic Synthesis

• Logic minimization.
• Technology dependent/independent minimization.
• Technology mapping.

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Physical Synthesis

• Placement.
• Routing.

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Logic Synthesis Problems for FPGAs

• How to synthesize a logic network to realize a
  given function.
• How to realize a logic network using FPGAs.
• How to optimize a given network for area and
  timing.
• How to synthesize routable circuits.
• How to solve these problems efficiently.

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Representation of Boolean Functions

• Truth tables.
• Factored forms SOP and POS.
• BDD.
• Boolean networks.

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Synthesis with Multiplexers
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Synthesis with Look-Up-Table (LUT)
d0 d1 d2 d3 d4 d5 d6 d7
HOW?
Boolean equations
y
LUT
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An Example of synthesis of the same function with
various components
XOR(a,b) ab ab
RAM
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Multilevel Logic Minimization

• MIS and SIS by UC Berkeley.
• Optimization for timing, area, and power.
• Technology independent.

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Technology Mapping for FPGAs

• Technology mapping is the process of binding
  technology dependent circuits to technology
  independent circuits.
• Technology mapping for FPGAs consists of two
  steps
• (1) decomposition and
• (2) covering.
• Technology mapper optimizes the final circuit by
  selecting sub-networks which are covered by LUTs.

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Technology Mapping for FPGAs

• LUTs have fixed number of inputs, k-input, which
  can implement logic functions up to k variables.
• Nodes and sub-networks with at most k inputs in a
  Boolean network are referred to feasible nodes
  and sub-networks else infeasible.
• Infeasible nodes need to be decomposed into a set
  of feasible nodes so that a circuit covering the
  network exists.

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Technology Mapping for FPGAs

• An FPGA-based technology mapper performs three
  tasks
• 1. Decomposition - It decomposes infeasible
  expressions into feasible ones.
  
• 2. Reduction - It groups small expressions into
  CLBs to promote sharing of resources.
  
• 3. Packing - It allocates CLBs to expressions
  that cannot be shared.

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Technology Mapping for FPGAs

• The optimization goals for FPGA-based technology
  mapping include
• The number of CLBs,
• The number of levels of CLB circuits, and
• Routable designs.

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Decomposition
Realization of a function
Before decomposition
After decomposition
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Decomposition

• Decomposition consists of three steps
• Identify divisors which are common to many
  functions.
• Introduce the divisor as a new node.
• Re-express existing nodes using the new nodes.

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An Example

• Given the expression
  
• f abacadabbcbdacbccdbdcd
• Suppose a factor found is
  
• p abcd
• f can be re-expressed based on p
  
• f p(abcd)

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Shannon Cofactoring

• The residue (cofactor) of a function
  f(x1,x2,..,xn) with respect to a variable xj is
  the value of the function for a specific value of
  xj.
• It is denoted by f(xj) for xj1 and by f(xj) for
  xj0.
• Ex. The residues, wrt a, of
  
• f(a,b,c,d) abbcbdacd are
• f(a) bcbdcd and f(a) b then
• f(a,b,c,d) af(a) af(a)

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Roth-Karp Decomposition

• Try to decompose a function into the form
• f(x,y) g(z1(x), z2(x),..,zt(x), y)
  
• x the bound set
  
• y free set
• Based on the concept of compatible classes.
• The xl_k_decomp operation in SIS for
  decomposition of k-input LUTs.
• Computationally expensive. It is useful for small
  designs with high degree of symmetry.

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Algebraic Decomposition

• Based on factored form representation and
  algebraic operations.
• Manipulating algebraic expressions as
  polynomials i.e., xi and xi are different
  variables.
• To reduce search, only common cube factors called
  kernels are used.
• Ex. x acbcbdce
  
• y abe and
• x cy bd

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AND-OR Decomposition

• Ensure that any infeasible node is decomposed
  into a set of feasible nodes.
• Can be used to decompose large infeasible nodes
  into infeasible nodes that are small enough to
  make an exhaustive search for disjoint
  decomposition.
• Ex. F abacbc can be decomposed into vab,
  wac, xbc, yvw and zyx F

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Decomposition

• Decomposition consists of three steps
• Identify divisors which are common to many
  functions.
• Introduce the divisor as a new node.
• Re-express existing nodes using the new nodes.

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An Example

• Given the expression
  
• f abacadabbcbdacbccdbdcd
• Suppose a factor found is
  
• p abcd
• f can be re-expressed based on p
  
• f p(abcd)

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Decomposition Techniques

• Disjoint decomposition.
• Shannon cofactoring.
• Roth-Karp decomposition.
• Algebraic decomposition.
• AND-OR decomposition.

• I have slides about all these methods.
• I teach 3 different classes about them

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Disjoint Decomposition

• Disjoint decomposition can be found by
• searching through all possible partitions of
  inputs to the infeasible nodes,
• and using well known methods, such as residues,
  to determine if each partition leads to a
  disjoint decomposition.
• Disadvantage the number of partitions grows
  exponentially with number of inputs to the
  infeasible nodes.

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Functional Decomposition
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Decomposition typical procedures
Decomposition of nodes
transformation
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Algorithm for decomposition
Serial
Parallel
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Parallel Decomposition
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Example of serial decomposition
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Parallel Decomposition
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Example of parallel decomposition
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Example of Parallel Decomposition Continued
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Balanced Method of Decomposition (Luba)
Parallel
Serial
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Method of puzzles
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experimental results (1)
Comparison of CLBs
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Experimental results (2)
Comparison of of levels/ of CLBs
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Experimental results (3)
Comparison with MAXPlus2 system
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Two-bit adder parallel-serial decomposition
S 105
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Two-bit adder serial-parallel decomposition
S 114
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Functional Decomposition
Gate Decomposition
Classical Decomposition
G logic gates H no change table of type fr
G table of type fr H table of type fr
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DES Algorithm
Sub-key
Expansion
permutation
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Realisation of S-boxes using DEMAIN
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Rijndael code
MAXPLUSII ? 305 cells of FLEX (4/1) 52
resources EPF 10K10 DEMAIN ? 162 cells 28
resources EPF 10K10
47a
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Eksperiment transcoder BIN ? BCD
Realization in system MAXPLUSII (Altera)
Metoda 3
32 (33) cell FLEX
Realization from truth table MAXPLUSII ? 131
cells DEMAIN ? 13 cells (!!!)
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Dekomposition of decision tables in machine
learning
Intermediate decision
Final Decision
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Example of decision table
Decision class
Marital Status
Attributes Age
Sex
profession
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Decision rules generated from a decision table
(Age, 20) ? (Marital_Status, Married) ? (Class,
1), (Age 16) ? (Class, 2), (Age,
17) ? (Class, 2), (Age, 20) ? (Marital_Status,
Single) ? (Class, 2), (Age, 25) ? (Gender,
Male) ? (Class, 3), (Age, 38) ? (Class,
3), (Age, 25) ? (Gender, Female) ? (Class,
4) (Age, 48) ? (Class, 4), (Age,
21) ? (Class, 5), (Age, 22) ? (Class,
5), (Age, 23) ? (Class, 5), (Age,
24) ? (Class, 5).
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Example
68 Data compression
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Decomposition-based FSM
A
C
B
Serial Decomposition
LUTs
G
register
EAB(s)
H
F H(A, G(B))
F H(A, G(B ? C))
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Synthesis Algorithm
1. Determine set A (preliminary encoding) 2.
Determine partitions P(A), Pg P(B) 3. Find
partition ?g ? Pg P(A) ? ?g ? PF (eventually
introduce set C) 4. Calculate functions G and H
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FSM Synthesis - An example
For s1
For s2
For s4
For s3
For s5
First task is to find partition PF from state
transition table
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. . . Example, contd
1. Determine set A (preliminary encoding) 2.
Determine partitions P(A), Pg P(B) 3. Find
partition ?g ? Pg P(A) ? ?g ? PF (eventually
introduce set C) 4. Calculate functions G and H
Preliminary Encoding
Second task is to find partition ? from state
transition table This gives us variable q1
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. . . Example, contd
A x1, x2, q1 B q2, q3 P(A)PF ((1)(6)
(2) (3,7)(4) (5)(8) (9,13) (10)(14)
(11)(15) (12)(16)) ?g 1, 2,
3 6, 7 ,8 4, 5, 13, 14, 15, 16 9, 10, 11,
12 Hence C x1
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Example, contd
In this new variant we create set B
B x1, q2, q3 P(A)PF ((1)(6) (2)
(3,7)(4) (5)(8) (9,13) (10)(14)
(11)(15) (12)(16))
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. . . Example, contd
x1 q2 q3
g
x1 x2 q1
G
REGISTER
H
q1 q2 q3
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Profit Estimation
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Materials used
Tadeusz LUBA
Wydzial Elektroniki i Technik Informacyjnych