MSO FPGA Slides

1
Simplifying MSO-based debugof designs with
Xilinx FPGAs
2
1) Route nets out to FPGA pins
FPGA
Agilent 9000 or 7000 Series
Pins
ExternalMSO
Probe points

• 1 signal per FPGA pin usually pin limited
• Requires design change to view new signals
• Manual management of physical and logical signal
  mapping to MSO digital channels and labels
• Equal time investment for each iteration

3
Manual Setup of Physical Connection Single pin
example
Connects to pod 1 channel 8 of the MSO
Goes to pin 10 of the mictor connect
Pin 6 of the FPGA
FPGA
Probe footprint
Oscilloscope
4
Manual Setup of Signal/Bus Names on MSO
Determine to which connector pin it was routed
Determine which logic channel is connected to
that pin
Look at schematic
Hand type eachname in MSO for every signal
routed to debug pins
Signal namein FPGA
Probe footprint
FPGA
Oscilloscope
5
Worlds First ( only) Integrated FPGA
Oscilloscope Application

• Incremental Real Time Internal Measurements
  without
• Stopping FPGA
• Changing the design
• Modifying design timing
• Quick MSO Setup
• FPGA pins to MSO digital channels
• Signal and bus names

MSO FPGA Dynamic Probe Application
6
MSO FPGA Dynamic Probe Application

• Options for Xilinx
• With 9000 Series MSOs
• With 6000/7000 Series MSOs

7
Datasheets, Design guide, FAQ, Resource
Calculator

• Options for Xilinx
• With 8000 Series MSOs www.agilent.com/find/8000-X
  ilinx
• With 6000 Series MSOs www.agilent.com/find/6000-X
  ilinx

8
FPGA Dynamic Probe for Xilinx
PC Board
FPGA
Insert ATC2 core with Xilinx Core Inserter
ATC2
9
Agilent Trace Core (ATC2)
ATC2
Output to FPGA pins for debug
4 - 128

• Up to 64 signal banks
• All banks have identical width (4 to 128 signals
  wide)

4 - 128
4 - 128
Selection MUX
4 -128
4 -128
clk
clk
Up to 16 digital channels on MSOs
JTAG Select
Change signal bank selection from MSO
10
Core Types for MSO

• State Core (most common usage)
• Best for functional debug in one time domain
• Minimal impact on timing
• MSO timing (asynchronous measurement)
• Measured on each FPGA clock cycle
• State trigger
• Trigger on pattern clock edge
• State waveform display
• Post-processing MSO feature
• Timing Core
• Best for measurements across multiple time
  domains
• Almost no impact on design timing
• Measurements include skew from routing path
  variancesGlitch detection
• Measured per MSO timing sample rate

11
State Coresalways have multiple pipeline stages
to minimize timing impact
Probe point
Output Pin
Customer Logic
FF
ATC2 (1 signal)
FF
FF
FF
12
Technology Walk Through (Xilinx Example)

• Xilinx Core Inserter
• Create core put it in design
• Agilent FPGA Dynamic Probe
• Pin and signal/bus setups
• Core control
• Taking measurements

13
Demo 1- Packet Flow Demo (MSO_comm_v9.bit)
Measure in 4 different parts of communication
system in a few seconds
14
Target System Xilinx XC2V250
JTAG
Mictor Connector (plug MSO cable into EVEN side)
15
2. FPGA Dynamic Probe SW application integrated
with Infiniium
4. Probe core output
3. Control access to new signals via JTAG
1. Insert ATC2 core in FPGA with Xilinx ChipScope
Pro
16
Define 1st Bank to View Transmit Side
External Data IN
Monitor
Serial Packets
8B/10B Encoder
Serial to Monitor State Machine
Serial from Monitor State Machine
State
TID Out
Serial Acks
State
TID
Ack ID
Master State Machine
8
7
RAM
Xilinx FPGA
Bank 0
Bank 3
Bank 2
Bank 1
Micro Blaze uP
TID State
Ack ID State TID out
Master State Mach.
Data In Out
Agilent Trace Core 2
MUX
External RAM
To MSO digital Connection (15 Pins for Debug
clk)
JTAG to MSO or PC
17
Define 2nd Bank to View Receive Side
External Data IN
Monitor
Serial Packets
8B/10B Encoder
Serial to Monitor State Machine
Serial from Monitor State Machine
TID Out
Serial Acks
State
Ack ID
Master State Machine
5
3
RAM
7
Xilinx FPGA
Bank 0
Bank 3
Bank 2
Bank 1
Micro Blaze uP
TID State
Ack ID State TID out
Master State Mach.
Data In Out
Agilent Trace Core 2
MUX
External RAM
JTAG to MSO or PC
To MSO digital Connection (15 Pins for Debug
clk)
18
Define 3rd Bank to View 8B/10B Encoder
External Data IN
Monitor
Serial Packets
8B/10B Encoder
Serial to Monitor State Machine
Serial from Monitor State Machine
State
TID Out
Serial Acks
State
TID
Ack ID
Master State Machine
5
10
RAM
Xilinx FPGA
Bank 0
Bank 3
Bank 2
Bank 1
TID State
Ack ID State TID out
Master State Mach.
Data In Out
Micro Blaze uP
Agilent Trace Core 2
MUX
External RAM
JTAG to MSO
To MSO digital Connection (15 Pins for Debug
clk)
19
4th Bank to View Master State Machine
External Data IN
Monitor
Serial Packets
8B/10B Encoder
Serial to Monitor State Machine
Serial from Monitor State Machine
State
TID Out
Serial Acks
State
TID
Ack ID
Master State Machine
15
RAM
Xilinx FPGA
Bank 0
Bank 3
Bank 2
Bank 1
Micro Blaze uP
TID State
Ack ID State TID out
Master State Mach.
Data In Out
Agilent Trace Core 2
MUX
External RAM
JTAG to MSO
To MSO digital Connection (15 Pins for Debug
clk)
20
4 Signal Banks
External Data IN
Monitor
Serial Packets
8B/10B Encoder
Serial to Monitor State Machine
Serial from Monitor State Machine
State
TID Out
Serial Acks
State
TID
Ack ID
5
Master State Machine
8
7
10
5
3
15
RAM
7
Xilinx FPGA
Bank 0
Bank 3
Bank 2
Bank 1
Micro Blaze uP
TID State
Ack ID State TID out
Master State Mach.
Data In Out
Agilent Trace Core 2
MUX
External RAM
JTAG to MSO
To MSO digital Connection (15 Pins for Debug
clk)
21
ChipScope Pro

• ILA logic analyzer viewer
• Core Inserter
• Post-synthesis insertion
• Core Generator
• Pre-synthesis core generation

Preferred design flow
22
Inserting ATC2 Cores
Design Entry
.v .
vhd
Functional Simulation
Synthesis
.
edf
Post-synthesis Simulation
.sfp .sdc
Insert ATC
2 Cores
Xilinx Core Inserter
Timing
Constraints
.
edf
.
ngo
.
cdc
Translate
(LUTs and nets)
.ucf
Map
(LUTs into Slices)
PlaceRoute
PlaceRoute
(FPGA resources)
(FPGA resources)
ISE
ISE
.
ncf
.
pcf
Static Timing
Timing Simulation
Static Timing
FPGA Editor
Analysis
Analysis
ISE
ISE
Minor Design Modifications FPGA Editor
Program FPGA
Program FPGA
ISE Impact
ISE Impact
.bit
mcs
.
Bitstream
PROM
FPGA
23
Set Core Parameters
Xilinx Core Inserter
Select Capture Mode
24
Xilinx Core Inserter Specify Signal Bank Grouping
25
Enable Integrated FPGA Dynamic Probe Application
26
Establish JTAG Communication Link(Between MSO
application and ATC2 core)
Reads scan chain and finds FPGA devices with ATC2
core
27
Import Signal Names
Reads .cdc file produced by Core Inserter
28
Auto Pin mapping
Map physical connection between core scope
Look for test pattern on each pin
PC Board
FPGA
1. Send training pattern over a ATC2 pin one
at a time
ATC2 with auto-setup
ATC3
JTAG
29
Auto-Pin Mapping
30
Graphical Pin Mapping
Probe footprint layout
MSO logic channel
ATC2 outputs (FPGA pins)
31
View Signals at Transmit Side
External Data IN
Monitor
Serial Packets
8B/10B Encoder
Serial from Monitor State Machine
Serial to Monitor State Machine
State
TID Out
Serial Acks
State
TID
Ack ID
Master State Machine
8
RAM
Xilinx FPGA
Bank 0
Bank 3
Bank 2
Bank 1
Micro Blaze uP
TID State
Ack ID State TID out
Master State Mach.
Data In Out
Agilent Trace Core 2
MUX
External RAM
To MSO digital Connection (15 Pins for Debug
clk)
JTAG to MSO
32
Select Bank to Activate
33
Measurement of Bank0 Signals/Buses
Time correlation with external events
Bank0 Signal Bus names
34
Measure Signals at Receive Side
External Data IN
Monitor
Serial Packets
8B/10B Encoder
Serial from Monitor State Machine
Serial to Monitor State Machine
State
TID Out
Serial Acks
State
TID
Ack ID
5
Master State Machine
RAM
Xilinx FPGA
Bank 0
Bank 3
Bank 2
Bank 1
Micro Blaze uP
TID State
Ack ID State TID out
Master State Mach.
Data In Out
Agilent Trace Core 2
MUX
External RAM
JTAG to MSO
35
Change to Measure Signals on Bank 1
36
Measurement of Bank1 Signals/Buses
Time correlation with external events
Bank1 signal and bus names
37
Triggering on Valid StatesATCK (clock) Pattern
guarantees valid state
This design transitions on positive clock edge,
so data should be stable on negative clock edges.
38
Trigger on Bus2 02H and D15 (atck) falling edge
clk
B2
39
Symbols Readouts
40
Transforming Timing (asynchronous) Waveforms
into State (synchronous) Waveforms
Invalid state (happens on rising edge when design
is transitioning)
41
State Clock D15 is the ATCK, data will be
stable on the falling edge
42
Resulting State Waveforms
Invalid states are filtered out (post-processing)
43
Demo 2- Up down counter (MSO_up_down_20MHz.bit)
Measure in 2 different parts of Xilinx system in
a few seconds
44
Target System Xilinx XC2V250
JTAG
Mictor Connector (plug MSO cable into ODD side)
45
2. FPGA Dynamic Probe SW application runs on PC
PC and MSO 6000 connect via LAN/USB/GPIB/etc
4. Probe core output
1. Insert ATC2 core in FPGA with Xilinx
ChipScope Pro
3. Control access to new signals via JTAG
46
ATC2 core configured with 2 Signal Banks
8 bit Count Down Design
8 bit Count Up Design
8
8
Xilinx FPGA
Bank 0
Bank 1
Agilent Trace Core 2
MUX
To MSO digital Connection (8Pins for Debug clk)
JTAG to MSO
47
Run the MSO FPGA Dynamic Application on PCPC
connects to MSO6000 via LAN, USB, or GPIB
48
FPGA Dynamic Probe
49
Load Design and Import Signal Names
50
Auto Pin Mapping
3. Map physical connection between core scope
2. Look for test pattern on each pin
PC Board
FPGA
1. Send training pattern over a ATC2 pin one
at a time
ATC2 with auto-setup
ATC3
JTAG
51
Pin Mapping
MSO signals do not connect here. ATCK (clock)
should be routed to any other place assessed by
MSO digital channels.
52
Select Bank 0 (count up clock)
53
Count Up
Bus Signal names
54
Select New Set of Internal Signals for Measurement
55
Resulting Measurement
Time correlation with external events
Bus Signal names
56
State Triggering Pattern ATCK edgeEliminates
the potential of triggering on invalid states
when FPGA design is transitioning
State Triggering
57
Measuring Valid States
Invalid state (FPGA design is transitioning on
positive clock edge
Valid states on falling clock edge
58
N5397A 8000 Series FPGA Dynamic Probe for Xilinx
59
N5406A 6000 Series FPGA Dynamic Probe for Xilinx