Electrical/Optical Issues in I/O CMOS Interfaces

1
Electrical/Optical Issues in I/O CMOS Interfaces
Thad Gabara Bell Laboratories Murray Hill, NJ
2
Electrical vs. Optical

• Interconnect length is a limiting aspect
• on-chip
• between chips
• between boards
• between cabinets
• between buildings
• cities and countries

thrend/BW
Electrical
Optical
3
Rents Rule
10K
ASIC
I/O k np
0.2 lt p lt 0.7 3 lt k lt 4
1K
Processor
I/Os
100
Memory
ISD June 1998, Tets Maniwa
107
108
109
1010
1011
1012
transistors (n)
4
Chip Interconnect Density
5000
4000
I/Os per die
solder bump - 225mm
3000
2000
Wire bond - 70mm
1000
Wire bond - 100mm
6
10
14
8
12
16
IBM, M. Nealon, Micro News
Die size (mm2)
5
Chip to Board Clock Rate
Multiplexed Bus
Clock rate (GHz)
Peripheral Bus
Source SIA 1997 Roadmap
00
95
05
10
Year
6
I/O Impact of Scaling CMOS

• Density in core is increasing
• Allows more data to be processed
• Need to keep up information
• transfer to/from core
• I/O transfer rates increasing
• Rents rule forces high pin count

7
Chip I/O Limitation

• Solder bump
• Process and packaging step differences
• CAD tools for chip partitioning
• Offers new potentials for system growth
• Allows for optimized process attachment

8
Solder Bump System Possibilities
Bi-CMOS
CMOS
Memory
Passives

• Shingling die
• Combine different optimized
• die together
• Allows formation of compact
• systems

9
Optical Chip Communication

• Process added step to CMOS
• SEED, VCSEL needs to cost compete
• with solder bump
• May offer backplane benefits
• Current High BW interfaces may benefit
• CPU-memory
• Switching networks

10
CDR Background

• single interconnect
• - coding schemes
• - contains both clock and data
• - bandwidth efficient connection
• at destination
• - perform post-processing
• to extract clock from data
• synchronize data at destination
• - using recovered clock

11
Clock and Data Recovery Performance Trend
projected Sonet target
10
1
data rate (GB/s)
0.1
Source International Solid-State Circuit
Conference
80
90
00
Year
12
Shadowing
die outline
gate

• Digital ASIC technique
• Use same layout around the frame
• Typically use a linear layout
• Small swing buffers are a problem

gate
Measured Data of Vol of 800mV swing(over several
lots) Avg DV s linear 136mV 31.6mV
13
Rotational Symmetry
die outline
gate

• Current matches
• Gate segments match

Measured Data of Vol of 800mV swing(over several
lots) Avg DV s linear 136mV
31.6mV Rot Sym 30mV 8.9mV
gate
14
Packaging

• Need to get power/ground to the chip

PGA 100 mil pitch
25
Area PGA 100 mil pitch
40
Area BGA 50 mil pitch
VL L di/dt introduces Ground Bounce
60
Direct Chip attach 20 mil pitch
IBM, M. Nealon, Micro News
Package size reduction achieves Lower L
smaller board area.
15
Ground Bounce Reduction
Equ Model
enable
L
K
Wide Bus
i

• PVT makes Rt/- 50

VL L di/dt

• Want to dampen the circuit
• Use transistor sizing to control
• transistor impedance - RC
• Insert impedance in VSS pad and
• inverse regulate ground
• impedance - RG

16
Digital Transistor Sizing

• Technique used over 2Gb/s
• Data path segregated from control
• Selector allows dynamic transistor sizing
• PVT (Process, Voltage, Temp) compensated (R and
  I)
• Controls impedance, performance, power, etc.
• Used in Ground Bounce buffers, HSTL and other
  buffers

17
Test Setup to Measure Bit Errors
From Pulse Generator 10MHz (0-3.6V)
From BERT
Ground Bounce Test Chip
80Mb/s (215-1)
Old or New
To BERT
N
N
16
60
0
C
C
60
60
0
(pF)
18
Bit Errors Generated
1B
100M
10M
1M
100K
Number of bit errors (OUT OF 4.8b BITS)
10K
1K
100
7 orders of improvement
10
0.7
0.8
0.9
1.0
0.1
0.2
0.3
0.4
0.5
1.1
0.6
1.2
Vamp (volts)
19
Computer/mProcessor Trends
100B
Connection Machine
10B
1B
CRAY XMP-4
RCA GaAS
CRAY I
100M
AMDAHL 5860
CDC 7600
VAX 8800
IBM 801
CDC 6800
AM2900
CRISP
IBM 3081
10M
CDC 6600
CLIPPER
IBM 3033
IBM 360/85
WE32200
WE32100
Instructions/sec
IBM STRETCH
MC68020
1M
MC68000
VAX 8200
UNIVACI
IBM 7090
INTEL 8086
100K
IBM 704
INTEL 4004
INTEL 8080
EDVAC
WHIRLWIND
10K
ILLIAC
MARK II COLOSSUS
ENIAC 30 TONS
1K
COLOSSUS
100
HARVARD MARK I
10
90
40
50
60
70
80
00
Year
20
Optical Chip Clocking

• Process added step to CMOS - maybe?
• Reduces skew
• Easier to synchronize chip

CMOS Chip
21
Skin Effect
d (pfms)-0.5

• Skin effect
• Affects the cross-sectional area
• The high-frequency components become
• more attenuated
• This causes pattern dependent effects which
• is know as intersysmbol interference

T
Below some T, the eye diagram of the data
degrades in W and H
H
W
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Optical Communication

• Skin effect doesnt occur
• Attenuation - 0.2db/km?
• Electrical attenuation -5db at a few GHz
• Electrical intersysmbol interference gone
• This is nice
• Circuits and techniques push the envelope
• ULSI gives transistors to use for I/O

23
Equalization

• Pre-emphasizes signal to compensate
• for attenuation
• Gives flat attenuation response from 0.2
• to 2GHz
• 4Gb/s over 100m

W. Dally and J. Poulton
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Conclusions

• Reviewed the SIA roadmap for I/O
• I/O Impact of scaling CMOS
• Circuit and system techniques
• Skin effect
• Equalization
• CMOS circuit design, infrastructure, CAD tools,
• ULSI, all favor pushing existing limits
• Tends to delay optical entry at the lowest level