Logic Gate Delay Modeling -III

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Logic Gate Delay Modeling -III

• Bishnu Prasad Das
• Research Scholar
• CEDT, IISc, Bangalore
• bpdas_at_cedt.iisc.ernet.in

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OUTLINE

• Delay Model History
• Static Timing Analysis (STA)
• Corner Models
• Drawback of Corner Approach
• Statistical Static Timing Analysis(SSTA)
• Summary

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Delay Model History
Courtesy Synopsys
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What to do with Delay Models?

• Timing analysis of the whole chip

Problem Given a circuit, find the path(s) with
the largest delay (critical paths)
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Timing Analysis

• Solution run SPICE and report the results of the
  simulation

• Problem SPICE is computationally expensive to
  run except for small-size circuits
• WANTED We need a fast method that produces
  relatively accurate timing results compared to
  SPICE

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Combinational Blocks

• Arrival time in Green
• Interconnect delay in Red
• Gate Delay in Blue

• What is the right mathematical object to
  represent this physical objects ?

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Combinational Blocks as DAG

• Use a labeled directed acyclic graph G ltV,Egt
• Vertices represent
• gates, primary inputs
• and primary outputs
• Edges represent wires
• Labels represent delays
• Now what do we do with this?

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Static timing analysis

• Arrival time A(v) for a node v is time when the
  signal arrives at node v

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Static timing analysis
C17 from ISCAS85 benchmarks
I1
1/2
2/3
O1
I2
2/4
I3
3/5
I4
2/4
O2
1/2
I5
1/2
I6

• All inputs are arrive at time 0
• Assuming all interconnects have 0 delay
• Each gate has rise/fall delay

• slack arrival time required arrival time
• ? paths with negative slacks need to be
  eliminated!

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STA can lead to false critical paths

• STA assumes a signal would propagate from a gate
  input to its output regardless of the values of
  other inputs

• What is critical path delay according to STA?

• Is this path realizable?
• No, actual delay is less than estimated by STA

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Signal Arrival Times
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Simultaneous Arrival Times
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Simultaneous Arrival Times
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Limitations of STA

• False path
• Simultaneous Arrival Time
• STA is done across all corners (Computationally
  Expensive)

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Corner Models

• Four types of Corner models
• Fast Corner
• Slow Corner
• Slow NMOS Fast PMOS
• Fast NMOS Slow PMOS
• Typical Corner

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Design Corners
FF
Fast
FS
TT
PMOS
FS
SS
Slow
Slow
Fast
NMOS
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Corner Table
Environmental parameters Environmental parameters Process parameter
Corner Voltage Temperature Vth Voltage
Fast Vnom10 -400C Vthnom-?Vth
Slow Vnom-10 1250C Vthnom?Vth
Typical Vnom 270C Vthnom
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Applications of Corners

• For Power and race condition like hold time use
  Fast corner
• For Delay simulation use Slow corner
• The other two corners are used for circuits which
  require precise sizing for proper functioning.
  Ex Memory and pseudo NMOS circuit.

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Limitations of Corner Models

• Worst case assumption is insignificant
• This leads to over design
• Hence more power, area and loss of performance
• Need more intelligent accounting of variations

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Gate Length Variation
Orshansky, et. al, IEEE Trans. On Sem.
Manufacturing, Feb 2004
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Environmental Variations Vdd
Anirudh Devgan, IBM, Mar 05
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Environmental Variations Temperature
Anirudh Devgan, IBM, Mar 05
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Statistical Static Timing Analysis
Ao max(Ai Dio , Aj Djo)
Delay is no longer Deterministic, it is a random
variable
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Addition Operation

• Addition operation The sum of two random number
  is convolutions of their probability functions.
• Ao Ai Dio
• Where Ci is the CDF of Ai .
• Pio is the PDF of Dio.

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Max Operation

• Max Operation The CDF of the maximum of two
  independent random variables is simply the
  product of the CDF of two variables
• Ao Max ( Ai , Aj )
• The CDF of node o is given by
• Co(t) Ci(t) Cj(t)

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Probability of Events
(a) A probabilistic event
(b) A probabilistic event group
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Propagating a Single event
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Propagating An event group
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Output of SSTA
C17 ISCAS Benchmark
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Summary

• Static Timing Analysis
• Limitations of STA
• Corner Models
• Limitations of Corner Models in Presence of
  Process Variation
• Statistical Static Timing Analysis

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References

• For SSTA
• J. J. Liou et.al, Fast Statistical Timing
  Analysis by Probabilistic Event Propagation, DAC
  pp. 661-666, June 2001.
• A. Devgan and C. Kashyap, Block-based Timing
  Analysis with Uncertainty, ICCAD, pp. 607-614,
  Nov. 2003.
• H.Chang, V. Zolotov, S. Narayan and C.
  Visweswariah, Parameterized Block-Based
  Statistical Timing analysis with Non-Gaussian
  Parameters, Nonlinear Delay Functions, DAC, pp.
  71-76, June 2005.
• For Corner Model
• N. H. E. Weste and D. Harris, CMOS VLSI Design,
  A circuits and Systems Perspective 3rd edition

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References

• Go to solvnet site https//solvnet.synopsys.com/am
  server/UI/Login
• and do an account for these materials
• CCS Models
• Xin Bao, Khusro Sajid, Elisabeth Moseley,
  Timing Sign-off using CCS Libraries at
  Qualcomm, Snug 2006 San Jose
• Peter Chih-Yang Pong, Steve H. Tsai, An
  Investigation of CCS, Snug Taiwan 2006
• CCS Timing Library Characterization Guidelines