Synthesis of asynchronous circuits from petri nets

1
Synthesis of asynchronous circuits from petri nets
2
Delay models (I)
A
C
B
Real (analog) behavior
Abstract behavior
A
B
C
Abstractions are necessary to define delay models
manageable fordesign, synthesis and
verification. Abstractions introduce
optimisticand pessimistic simplifications that
must be carefully taken into account.
3
Delay models (II)

• Separation between functionality and timing
  Muller
• Every gate has a zero-delay atomic evaluator
  (Boolean function)
• A delay is associated to every output (gate delay
  model)or every input (wire delay model)
• Delays can be
• Unbounded (arbitrary finite delays)
• Bounded (within given min/max bounds)

Gate delay model
Wire delay model
4
Delay models (III)

• Gate delay model delays in gates, no delays in
  wires
• Wire delay model delays in gates and wires

5
Delay models (IV)

• Speed-independent circuithazard-free under the
  unbounded gate delay model
• Delay-insensitive circuithazard-free under the
  unbounded wire delay model
• Quasi-delay -insensitive circuitdelay-insensitiv
  e with some isochronic forks

6
Speed-independent model

• Pessimistic, since delays are typically bounded
• Optimistic, since it assumes isochronic
  forks(negligible skew wrt the receiving gate
  delays)
• Efficient synthesis methods exist

Isochronic fork
7
Fundamental mode of operation
Inputs
Outputs
Circuit
d
d
Huffman 1964 The circuit/environment interact
with two phases (1) The environment sends inputs
to the circuit (2) The circuit computes the
outputs and the state signals The environment
does not send new inputs until the circuit
stabilizes Normal Fundamental Mode Only one
input changes at each communication cycle
8
Input/Output mode of operation

• Computation and communication can overlap
  (according to some specified protocol)
• Event-based specification models are often used
  to describe the behavior (e.g., Petri nets).

This tutorial will cover the synthesis of
speed-independentcircuits that work under the
I/O mode of operationand are specified using
Petri nets.
9
Delay models for async. circuits

• Bounded delays (BD) realistic for gates and
  wires.
• Technology mapping is easy, verification is
  difficult
• Speed independent (SI) Unbounded (pessimistic)
  delays for gates and negligible (optimistic)
  delays for wires.
• Technology mapping is more difficult,
  verification is easy
• Delay insensitive (DI) Unbounded (pessimistic)
  delays for gates and wires.
• DI class (built out of basic gates) is almost
  empty
• Quasi-delay insensitive (QDI) Delay insensitive
  except for critical wire forks (isochronic
  forks).
• In practice it is the same as speed independent

BD
SI ? QDI
10
Outline

• Overview of the synthesis flow
• Specification
• State graph and next-state functions
• State encoding
• Implementability conditions
• Speed-independent circuit
• Complex gates
• C-element architecture
• Review of some advanced topics

11
Book and synthesis tool

• J. Cortadella, M. Kishinevsky, A. Kondratyev,L.
  Lavagno and A. Yakovlev,Logic synthesis for
  asynchronouscontrollers and interfaces,Springer-
  Verlag, 2002
• petrifyhttp//www.lsi.upc.es/petrify

12
Design flow
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
13
Specification
x
x
y
y
z
z
x-
z
x
y
z-
y-
Signal Transition Graph (STG)
14
Token flow
15
State graph
16
Next-state functions
17
Gate netlist
x
y
z
18
Design flow
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
19
VME bus
Bus
Data Transceiver
Device
D
LDS
DSr
VME Bus Controller
DSw
LDTACK
DTACK
20
STG for the READ cycle
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
LDS
DSr
VME Bus Controller
LDTACK
DTACK
21
Choice Read and Write cycles
DSr
DSw
LDS
D
LDTACK
LDS
D
LDTACK
DTACK
D-
DSr-
DTACK
D-
DSw-
22
Choice Read and Write cycles
23
Circuit synthesis

• Goal
• Derive a hazard-free circuitunder a given delay
  model andmode of operation

24
Speed independence

• Delay model
• Unbounded gate / environment delays
• Certain wire delays shorter than certain paths in
  the circuit
• Conditions for implementability
• Consistency
• Complete State Coding
• Persistency

25
Design flow
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
26
STG for the READ cycle
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
LDS
DSr
VME Bus Controller
LDTACK
DTACK
27
Binary encoding of signals
DSr
DTACK-
LDS
LDTACK-
LDTACK-
LDTACK-
DSr
DTACK-
LDS-
LDS-
LDS-
LDTACK
DSr
DTACK-
D
D-
DSr-
DTACK
28
Binary encoding of signals
DSr
DTACK-
10000
LDS
LDTACK-
LDTACK-
LDTACK-
DSr
DTACK-
10010
LDS-
LDS-
LDS-
LDTACK
DSr
DTACK-
10110
01110
10110
D
D-
DSr-
DTACK
(DSr , DTACK , LDTACK , LDS , D)
29
Excitation / Quiescent Regions
30
Next-state function
0 ? 1
0 ? 0
1 ? 1
1 ? 0
31
Karnaugh map for LDS
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
0
0
0
0/1?
-
-
32
Design flow
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
33
Concurrency reduction
LDS
LDS-
LDS-
LDS-
10110
10110
34
Concurrency reduction
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
35
State encoding conflicts
LDS
LDTACK-
LDS-
LDTACK
10110
10110
36
Signal Insertion
LDTACK-
LDS
LDS-
LDTACK
101101
101100
D-
DSr-
37
Design flow
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
38
Complex-gate implementation
39
Implementability conditions

• Consistency
• Rising and falling transitions of each signal
  alternate in any trace
• Complete state coding (CSC)
• Next-state functions correctly defined
• Persistency
• No event can be disabled by another event (unless
  they are both inputs)

40
Implementability conditions

• Consistency CSC persistency
• There exists a speed-independent circuit that
  implements the behavior of the STG(under the
  assumption that ay Boolean function can be
  implemented with one complex gate)

41
Persistency
a
c
b
is this a pulse ?
Speed independence ? glitch-free output behavior
under any delay
42
(No Transcript)
43
ER(d)
ER(d-)
44
ab
cd
00
01
11
10
0
0
0
0
00
1
0
01
1
1
1
1
11
1
10
Complex gate
45
Implementation with C elements
? S ? z ? S- ? R ? z- ? R- ?

• S (set) and R (reset) must be mutually exclusive
• S must cover ER(z) and must not intersect
  ER(z-) ? QR(z-)
• R must cover ER(z-) and must not intersect
  ER(z) ? QR(z)

46
ab
cd
00
01
11
10
0
0
0
0
00
1
0
01
1
1
1
1
11
1
10
S
d
C
R
47
but ...
S
d
C
R
48
Starting from state 0000 (R1 and S0)
a R- b a- c S d
S
d
C
R
49
ab
cd
00
01
11
10
0
0
0
0
00
1
0
01
1
1
1
1
11
1
10
Monotonic covers
50
C-based implementations
c
d
C
b
a
c
weak
c
d
weak
d
a
a
b
generalized C elements (gC)
51
Speed-independent implementations

• Implementability conditions
• Consistency
• Complete state coding
• Persistency
• Circuit architectures
• Complex (hazard-free) gates
• C elements with monotonic covers
• ...

52
Synthesis exercise
1011
0011
0111
Derive circuits for signals x and z (complex
gates and monotonic covers)
53
Synthesis exercise
1011
wx
yz
00
01
11
10
-
1
1
0
00
0011
-
1
1
0
01
-
0
0
0
11
-
1
1
0
10
0111
Signal x
54
Synthesis exercise
1011
wx
yz
00
01
11
10
-
0
0
0
00
0011
-
0
0
0
01
-
1
1
1
11
-
1
0
0
10
0111
Signal z
55
Logic decomposition example
y-
y-
1001
1011
z-
w-
1000
0001
w
y
x
w-
z-
z-
w-
w
1010
0000
0101
0011
w-
z-
y
x
y
x
x-
0010
0100
x-
y
x
z
0110
0111
z
56
Logic decomposition example
x
y-
w
y
1001
1011
z-
z
w-
y
1000
0001
w
y
z
x
w-
z-
x
w
1010
0000
0101
0011
w-
z-
y
x
w
y
z
0010
0100
x-
z
y
x
z
y
0110
0111
x
z
y
57
Logic decomposition example
s1
x
y-
w
s
1001
1011
y
z-
s-
z
w
1001
1000
z-
s-
y
w-
x
w
0011
0001
1000
1010
y
s-
x
w-
z-
w
x-
y
z
0000
0101
1010
z
w-
z-
y
x
0111
0010
0100
y
s
y
x
x
z
s0
z
0111
y
0110
58
Logic decomposition example
s1
y-
y-
1001
1011
z-
s-
s-
w
1001
1000
z-
s-
y
w-
z-
w-
w
0011
0001
1000
1010
y
s-
x
w-
z-
x-
0000
0101
1010
y
x
x-
w-
z-
y
x
0111
0010
0100
s
s
y
x
z
s0
z
0111
0110
59
Speed-independent Netlist
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
60
Adding timing assumptions
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
61
Adding timing assumptions
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
62
State space domain
DSr
LDTACK-
63
State space domain
DSr
LDTACK-
64
State space domain
DSr
LDTACK-
Two more unreachable states
65
Boolean domain
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
0
0
0
0/1?
-
-
66
Boolean domain
LDS 1
LDS 0
-
-
-
0
1
-
0
1
-
-
-
-
-
-
-
-
1
1
1
-
-
-
-
-
0
0
-
0
0
1
-
-
One more DC vector for all signals
One state conflict is removed
67
Netlist with one constraint
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
map
csc
DSr
LDTACK
68
Netlist with one constraint
DTACK-
DSr
LDS
LDTACK
D
DTACK
DSr-
D-
LDS-
LDTACK-
D
DTACK
LDS
DSr
LDTACK
69
Signal insertion

• New signals need to be inserted to solve some
  synthesis problems (e.g., state encoding, logic
  decomposition)
• For each signal s, the events s and s- must be
  inserted while preserving certain behavioral
  properties (consistency, persistency).
• Each new signal determines a new partition of
  states (s0, s1)

70
Signal insertion
s
s0
s1
s-
71
From state graphs to Petri nets

• A state graph may require transformations to meet
  certain properties (e.g., state encoding).
• The visualization of a state graph is not very
  informative. Event-based specifications
  explicitly represent the relations between
  events.
• Resort to the theory of regions

72
From state graphs to Petri nets
a
0
1
e
f
a
b
3
d
c
d
d
2
5
d
c
4
b
e
f
e
f
6
c
Region 2,3
73
From state graphs to Petri nets
a
0
1
e
f
a
b
3
d
c
d
d
2
5
d
c
4
b
e
f
e
f
6
c
Region 1
74
From state graphs to Petri nets
a
0
1
e
f
a
b
3
d
c
d
d
2
5
d
c
4
b
e
f
e
f
6
c
Not a region 3,5
75
From state graphs to Petri nets
a
0
1
e
f
a
b
3
d
c
d
d
2
5
d
c
4
b
e
f
e
f
6
c
Region 0,3,5
76
Theory of regions

• Region all arcs of any event have the same
  relationship with the region (enter, exit, no
  cross).
• Minimal region not included in any other region
• Pre-/post-region of an event region such that
  the event exits/enters the region
• Property excitation closure
• The intersection of all pre-regions of an event
  is the excitation region of the event

77
OTHER paradigms

• Thanks to Steve Nowick (Columbia Univ.)

78
Burst-Mode Specifications

• How to specify burst-mode behavior?

current state
A C-/ Y- Z
input burst/ output burst
next state
inputs
outputs
A
X
B
Y
Hazard-Free Combinational Network
C
Z
state
output burst
input burst
(several bits)
79
Burst-Mode Specifications
Initial Values ABC 000 YZ 01

• Example Burst-Mode (BM) Specification

A C/ Z-
- Inputs in specified input burst can arrive
in any order and at any time
A B/ Y Z-
- After all inputs arrive, generate output burst
C-/ Z
B- C/ Z
Note -input bursts must be non-empty
(at least 1 input per burst) -output bursts
may be empty (0 or more outputs per burst)
C/ Y
C-/ --
A-/ Y-
80
Burst-Mode Specifications

• Extended Burst-Mode (XBM)
• Yun/Dill ICCAD-93/95

ok Rin/ FRout
ok- Rin/ --
FAin Rin/ FRout-
New Features
FAin- Rin/ Aout
ltCnd-gt Rin-/ Aout-
1. directed dont cares (Rin) allow
concurrent inputs outputs
2. conditionals (ltCndgt) allow sampling
of level signals
ltCndgt Rin-/ Aout- FRout
Rin FAin-/ Aout
Handles glitchy inputs, mixed sync/async
inputs, etc.
Rin FAin/ FRout-
81
Syntax-directed translation

• 2-Place Ripple Register ( FIFO) van Berkel

Intermediate Handshake Circuit
Tangram Program
proc (a?T b!T) begin x0, x1 var T
forever do b! x1 x1 x0 a? x0 od end
82
A Larger Example
Intermediate Handshake Circuit
83
Background Channel-Based Communication
Channel A

• Components communicate using 4-phase
  handshaking
• O1 initiates communication
• O2 completes communication
• Channel impltn. gt use 2 wires
• req gt start operation
• ack gt operation done
• ( can be extended to handle data)

Active phase
Return-to-zero (RTZ) phase
84
Handshake Components Sequencer

• 2-Way Sequencer activated on channel P then
  activates 2 processes in sequence on channels A1
  and A2

Process X1
A1
SEQ
P
A2
Process X2
Operation X1 X2
Goal activate two sequential processes (i.e.
operations)
85
Handshake Components PAR Component

• PAR Component activated on channel P
• then activates 2 processes in parallel on
  channels A1 and A2

Process X1
A1
P
PAR
A2
Process X2
Operation X1 X2
Goal activate two parallel processes
86
Intermediate Representation
procedure Buf1 ( input i byte output o
byte) is local variable x byte begin loop
begin i -gt x o lt- x end end
Tangram Spec
Handshake Circuit
87
Conclusions

• STGs have a high expressiveness power at a low
  level of granularity (similar to FSMs for
  synchronous systems)
• Synthesis from STGs can be fully automated
• Synthesis tools often suffer from the state
  explosion problem (symbolic techniques are used)
• The theory of logic synthesis from STGs can be
  found in

J. Cortadella, M. Kishinevsky, A. Kondratyev, L.
Lavagno and A. Yakovlev,Logic Synthesis of
Asynchronous Controllers and Interfaces,Springer
Verlag, 2002.