Breaking the Cost Barrier

1
Breaking the Cost Barrier

• Low-Cost, High-Speed
• Programmable Solutions

No Compromises
2
Xilinx Breaks the Programmable LogicCost Barrier
Programmable logic is the most cost-effective
logic solution!

• FPGAs lt3
• CPLDs near 1

• Device cost

• Performance

• gt100 MHz

• Features

• In-system re-programmable
• FPGA RAM
• Boundary scan
• Low power

100K units, slowest speed, lowest density,
cheapest package, mid-1999
3
Programmable Logic Reduces All Cost Factors

• Development system
• NRE
• Learning time
• Design time
• Risk
• Flexibility
• Testing
• Time-to-market

• Starts at 95
• 0
• Hours
• Hours to days
• Zero with Core solutions
• Low
• Reprogram (even over web)
• 100 factory tested
• Days to weeks

4
AgendaBreaking the Cost Barrier

• Example design challenge - PC99
• solution alternatives
• FireWire interface challenge
• SpartanXL FPGA solution
• Foundation software solution
• SDRAM controller challenge
• XC9500XL CPLD solution
• Foundation and WebFITTER software

5
High Volume, Cost Sensitive Challenges Are Met

• Programmable solutions now meet high-volume
  needs
• low cost
• fast time-to-market
• Example applications
• consumer products
• personal computers
• PC peripherals
• PC standards drive these applications
• measure the solution against PC requirements

6
Example Applications
PC Peripherals
Network interface cards
Mobile computing
PCS phones
Docking stations
SDRAM Controllers
Modems
FireWire
I/O interface boards
Ethernet adapters
Household appliances
Gate array replacement
Handsets
Device bay
Flight simulators
Instrumentation
ADSL
Home theatre
Discrete logic integration
Personal electronics
Digital TV
Network routers
RAID
HDTV
Web TVs
PC99
Video compression
Electronic toys
Network computers
Set-top boxes
ISDN
Satellite decoders
Video cameras
Compact PCI
RISC interface
Monitors
LCD projectors
Cell phones
DSS
Credit card readers
Digital cameras
PCMCIA
Digital Hi-Fi
Robotics
CAN bus
Network computers
Video phones
Graphics acceleration
Badge readers
Fax machines
DVD
Music synthesizers
Cable modems
Hubs
IIC
Optical drives
Security systems
Security systems
PCI
Digital monitors
Color correction
Card bus
Arcade games
Modems
VCR
Hard drives
Process controllers
USB
Audio
LANs
Video editing
Consumer electronics
Internet appliances
DSP
Click drives
Printers
Medical imaging
Digital VHS
Video capture cards
MPEG/JPEG
Video conferencing
Satellite base stations
Camcorders
Handheld scanners
Test equipment
POS terminals
Voice processing
Multimedia
Personal digital assistants
CDROM drives
GPS
Video conferencing
Digital audio mixing desks
Bar code readers
Reconfigurable computing
Telephony
Digitizers
PCS ground stations
Automotive cabin controls
Fiber optics
PBX switches
Copiers
PC network cards
Imaging systems
7
Programmable Logic Challenge PC99 Example

• Intel/Microsoft guidelines for PCs built
  1999-2000
• Minimum 300 MHz processor, 32 MB RAM
• Eliminates ISA bus
• 12 MHz USB ports for mouse, keyboard
• 400 Mbps FireWire ports for drives, audio, and
  video
• Device Bay recommended for upgrading USB or
  FireWire peripherals without opening the box
• Mobile PC requires small size, low power

8
Xilinx Solution for PC99 in PCs and Peripherals
Peripherals
SpartanXL USB interface/ FireWire interface
Personal Computer
XC9500XL SDRAM Controller
Memory
Processor
USB FireWire
Device Bay
USB, FireWire interfaces
9
FPGAs and CPLDs OftenCo-Exist in the Same System

• FPGAs excel at
• higher density
• pipelined logic
• FIFOs, register files
• using RAM
• CPLDs excel at
• deterministic performance
• fast pin-to-pin speed
• state machines
• wide decoding

10
Xilinx Low-Cost SolutionsSpan the Density Range
FPGAs
CPLDs
11
FPGA ChallengeFireWire Example

• FireWire part of PC99 spec is used to demonstrate
  the benefits of Xilinx FPGAs
• IEEE 1394 standard
• based on Apples original definition of FireWire
• High speed serial bus
• 400 Mbits/s required for PC99 increasing to 3.2
  Gbits/s
• For emerging consumer electronics
• digital camcorders, DVD players, digital VCRs,
  HDTV, set-top boxes, video conferencing
• For traditional PC peripherals
• hard drives, printers, scanners, modems

12
FireWire Link Layer Interface Transmit Section

• Physical layer operates at full 400 MHz data
  transfer rate
• serial-to-parallel conversion drops data rate to
  50 MHz for back-end link layer
• Link Layer includes CRC generation and FIFOs

50 MHz
Physical Layer
Receive
400 MHz FireWire
Link Layer Interface
Transmit
8

CRC
Request/ Data
FIFOs
Application Interface
PHY Interface
Cycle Start
Core State Machine
13
Challenges Facing the Design Engineer
Design complexity
HDL entry
Design time
Flexibility for an evolving standard
Cost control
High performance FIFOs
Low power
Design tools
Design cycle time
14
Potential Solutions

• Discrete logic
• not practical approach any longer
• few available 3.3V/2.5V devices available
• Chip sets
• few available
• expensive
• Custom ASIC
• long design cycle
• costly to rework
• Programmable Logic

15
Spartan Series FPGAs Provide Solution

• Reprogrammable instant updates
• Flexibility and design complexity
• feature-rich programmable architecture
• High performance gt100 MHz parallel logic
• Design tools
• established, easy-to-use development tools
• complete software support and extensive cores
  (IP)
• Cost control
• advanced process technology for small, low cost
  die
• streamlined manufacturing provides total cost
  management

16
Xilinx FPGA Architecture Benefits

• SRAM programming cells
• easy design changes
• On-chip distributed SelectRAM memory
• efficient FIFOs
• Segmented routing
• high speed and low power
• Dedicated carry logic
• high speed counters and arithmetic

17
Reprogrammability

• Fast time to market
• immediate design changes
• no cost penalty for mistakes and updates
• Immediate production
• no conversion costs
• off-the-shelf
• no inventory risk
• 100 tested
• streamlined Xilinx testing reduces costs

18
High Performance FIFOsUsing SelectRAM Memory

• Any logic block can be used as SelectRAM memory
• Distributed RAM provides high performance
  solutions
• Features
• synchronous write, asynchronous read
• separate read port in dual-port mode for FIFOs

19
CLB RAM Provides 16xthe Storage of Flip-Flops

• Configurable Logic Block (CLB) storage
• SelectRAM 32 bits per CLB
• flip-flops 2 bits per CLB
• 100-784 CLBs in SpartanXL series

CLB
CLB
D1
2 bits
32 bits
Q1
D1
D
Q
Logic
A0
O1
A1
A2
Q2
D2
D
Q
A3
A4
CLK
WE
20
High Speed Low Power Through Segmented Routing

• Short interconnect segments are combined to
  create custom routing paths automatically
• Minimizes capacitance
• higher speed lower power
• Internal three-state buffers for
  integrated buses
• Dedicated clock routing for high speed and
  low skew

Long Lines
CLB
CLB
General Purpose
Switch Matrix
Switch Matrix
CLB
CLB
21
SpartanXL Low Power

• All Xilinx FPGAs minimize power by using
  segmented interconnect
• 3.3V SpartanXL FPGAs consume less than half the
  power of 5V Spartan FPGAs
• Power Down mode reduces quiescent current to
  100 mA

Spartan
Spartan XL
Power Down
22
Fast Arithmetic and Counters

• Increased arithmetic density and speed
• dedicated carry logic in CLBs
• dedicated carry routing
• 16 bits at 120 MHz
• DSP functions more efficient in FPGAs than
  dedicated DSP processors
• twice the speed
• one-tenth the cost

carry
CLB
carry
CLB
23
SpartanXL 3.3-V Series

• No Compromises

24
SpartanXL Implementation

• Implement FIFO part of FireWire design as an
  example
• 50 MHz required

25
Xilinx Design Tools Support Your Methodologies
Evolution of Programmable Logic Design
VHDL or Verilog Synthesis Single designer
Cores, HDL, Design reuse, Behavioral
compiler Larger design teams
Synthesis and Cores Small team
Equations/ Schematic Single designer
Future
TIMELINE
Timing-Driven Place and Route
HDL Back Annotation
Tighter ties with synthesis vendors
Module Compile
Module Guide
Evolution of Programmable Logic Tools
26
Xilinx Foundation Series

• Ready-to-Use
• Push-button, high- performance design
• Mixed-level design
• easy schematic entry
• superior HDL solution
• Low-cost Base system supports all SpartanXL and
  XC9500XL devices

27
Instant Productivity

• Intuitive GUIs, with design wizards
• Mixed-level, mixed-language design environment
• Push-button design flows
• Intuitive project management

28
Best-in-ClassEDA Technology
Aldec Design Entry Tools
Optional RTL HDL Simulation
Synopsys Synthesis
Aldec Gate-Level Simulator
Xilinx Implementation tools (including A.K.A.
Speed Technology)
K-Paths Enhanced Static Timing Analyzer
29
Unified Design Environment
Standard Windows Pull-down Menus
Standard Windows Tool Bar
Foundation Flow Engine Window with Content, and
Report Tab
Flow Button
Design File Management Window with File, and
Version Tabs
Status Indicator
Console Window with Error, Warning, and Messages
Tabs
30
Foundation On-Line Help

• On-line help includes link to support.xilinx.com
• dedicated support web site
• result of Silicon Xpresso initiative

31
Superior HDL Solution Design Creation

• VHDL Verilog HDL Design Capabilities
  Including
• graphical state diagram editor
• powerful HDL editor with integrated language
  assistant
• LogiBLOX and CORE Generator instantiations
• HDL tutorials from Esperan
• Xilinx Verilog CBT course

Language Assistant
Language Assistant
Graphical State Editor
Graphical State Editor
32
Mixed-Level Design
Design Wizard automates the process of adding an
HDL symbol into a schematic.
HDL Design becomes as easy as schematic entry
with drop in blocks of HDL. HDL editor directly
associated with new schematic object.
HDL Design becomes as easy as schematic entry
with drop in blocks of HDL. HDL Editor directly
associated with new schematic object
33
Push-Button Synthesis
or
Foundation Pull Automation runs both Synthesis
and Implementation tools after the push of a
single button and completion of the synthesis /
implementation dialog.
X
X
Optional HDL constraint entry and TimeTracker
GUIs illustrate estimates of your designs
critical paths using an intuitive spreadsheet
format
34
Push-Button Performance

• Xilinx A.K.A. Speed technology
• high quality of results
• short run time

35
Design Results

• All constraints were met.
• Timing summary
• Timing errors 0 Score 0
• Constraints cover 1649 paths, 94 nets, and 516
  connections (100.0 coverage)
• Design statistics
• Minimum period 19.025ns (Maximum
  frequency 52.562MHz)

36
Beyond Push-Button Implementation

• FPGAs allow for extensive optimization through
  creative design and implementation
• Standard library counter runs at 120 MHz in
  SpartanXL using default options
• Asynchronous frequency counter runs at over 400
  MHz!
• Uses extensive pre-scaling

37
AllianceCORE Solutions

• Core solutions leverage the optimization and
  verification of third parties
• FireWire AllianceCORE design and evaluation board
  available from Integrated Intellectual Property
• Fully tested and verified for Xilinx FPGAs
• pennies per chip in volume

CRC
Request/ Data
FIFOs
PHY Interface
Cycle Start
Core State Machine
Application Interface
Packet Analyzer
Data
Register Set
Status
CRC Check
38
Core Generator Delivery System
Parameterized Cores
Data sheets
CoreLINX Web Mechanism to Download New Cores

• SystemLINX
• Third Party System
• Tools Directly Linked
• With Core Generator

Free Software Free Cores Included (Cores offer
over 1,000,000 permutations!)
39
PCI32 Spartan - Lowest Cost PCI
20
Supported devices XCS20XL XCS30XL XCS40XL
External PLD7K Gates
15
Standard ChipPCI Master I/F
Component cost 100K units
10
XCS20XL-4 TQ144
7K Gates Logic
5
Power by
PCI Master I/F
Standard Chip
Solution lt7
40
High-Value Applications with Spartan
Prices are for 100K units, plastic package
41
SpartanXL Benefits

• Fast time-to-market
• user programmable
• Low cost
• Features for complex logic
• high speed
• low power
• Easy to use
• fully supported by Xilinx and third-party
  software

42
CPLD Solution for PC99 SDRAM Controller Example
SpartanXL USB interface/ FireWire interface
Personal Computer
XC9500XL SDRAM Controller
Memory
Processor
USB FireWire
Device Bay
USB, FireWire interfaces
43
Challenges Facing the Design Engineer
Small package
3.3V/2.5V
Design time
HDL entry
100 MHz minimum speed
Board layout before design is complete
Cost control
Multiple SDRAM protocols
Minimal programming overhead
Sufficient address width
Three-state flexibility
Clock flexibility
Resources for future expansion
44
Memory Interface Block Diagram
Address230
Address110
CPLD SDRAM Controller
Clock
CS
Reset
RAS
Microprocessor
Write
CAS
SDRAMs
WE
Data150
Complete SDRAM Controller in a single CPLD
45
SDRAM Interface Close-up
ADDR2312
Address230
ADDR110
ADDR110
Data150
Address Decode
Chip Select
Mode Register
Refresh Counter
CS
Clock
RAS
State Machine
Reset
CAS
Write
WE
46
3.3-V XC9500XL Solution

• Optimized for 3.3-V systems
• compatible levels with 5.0/2.5V
• no power sequencing restrictions!
• Meets performance requirements
• high fMAX 200 MHz
• fast tPD 4 ns
• Best ISP/JTAG support in industry
• Best pinlocking in industry
• Advanced packaging - New CSPs !

47
XC9500XL Architecture

• New extra-wide function block inputs

48
XC9500XL Function Block

• Handles SDRAM address width with 54 inputs
• highest function block fan-in on fast CPLDs

49
XC9500XL Macrocell
Flexible clocking and three-state control
Local macrocell clock inversion control
50
XC9500XL Special System Designer Benefits

• Input hysteresis
• Fully compliant ISP/JTAG guarantees no ISP lock
  out
• No power sequencing restrictions
• Hot plug-in

51
Advanced CSP Packaging
Supports high-growth market segments Communicatio
ns, Computers, Consumer
Uses standard IR techniques for mounting to PC
board
52
XC9500XL Solution Meets Design Challenges

• 3.3/2.5V electrical compatibility
• no power-sequencing restriction
• Chip scale packaging
• Pin-locking allows design change flexibility
• No programmer necessary with JTAG-based
  programming
• Fast design time
• VHDL, Verilog or ABEL design entry

53
XC9500XL Solution Meets Design Challenges

• 100 MHz minimum speed
• 133 MHz met
• Multiple SDRAM protocols
• 48 remaining capacity
• Sufficient address width (32 or 64 bit)
• Any clocking and three-state option needed
• Abundant resources for future expansion
• Low cost

54
XC9500XL 3.3-V Family
55
XC9500XL Design Software

• XC9500XL fitters in all Xilinx standard software
  packages
• Support for schematics, Verilog, VHDL, ABEL
• Exemplar, Synopsys, Synplicity, and others
• JTAG downloader for both FPGAs and CPLDs
• WebFITTER simplifies test-driving CPLDs

56
CPLD Design on the Web
1
2
3
Design in VHDL, Verilog, ABEL, etc.
Submit design to WebFITTER
Evaluate results

• No software to load
• no user resources needed
• no license
• WebFITTER software always current
• no upgrade CDs
• Runs fast on network (minutes)

57
WebFITTER Intro Page
58
WebFITTER Activity Report
59
WebFITTER Report File
60
SDRAM Controller Implementation in XC9500XL

• Results for XC95144XL
• Utilization
• 52 of capacity available for other logic
• Speed
• faster than required for 133 MHz clock
• Lowest-cost solution
• Compare to chip sets and other CPLDs

61
Simple Fast Low-Cost CPLD Solutions
Variances In Interfaces SDRAM (i.e. Bank vs.
SIMM) Unique System Back-End

• Isolates user from interface issues
• critical signal timing
• electrical interfacing
• control signal sequencing (state machine design)

62
New XC9500XV 2.5V Family
XC9500XV
9536XV
9572XV
95144XV
95288XV
Macrocells
36
72
144
288
Usable Gates
800
1600
3200
6400
t
(ns)
1H99
5
7
10
10
PD

2H99
3.5
4
4
5
f
200
178
178
151
SYSTEM
Packages
44PC (34)
44PC (34)
(Max. User
64VQ (36)
64VQ (52)
I/Os)
100TQ (72)
100TQ (81)
144TQ (117)
144TQ (117)
208PQ (168)
BGA
256BG (168)
CSPs
48CS (36)
48CS (36)
144CS (117)
63
Example Applications
PC Peripherals
Network interface cards
Mobile computing
PCS phones
Docking stations
SDRAM Controllers
Modems
FireWire
I/O interface boards
Ethernet adapters
Household appliances
Gate array replacement
Handsets
Device bay
Flight simulators
Instrumentation
ADSL
Home theatre
Discrete logic integration
Personal electronics
Digital TV
Network routers
RAID
HDTV
Web TVs
PC99
Video compression
Electronic toys
Network computers
Set-top boxes
ISDN
Satellite decoders
Video cameras
Compact PCI
RISC interface
Monitors
LCD projectors
Cell phones
DSS
Credit card readers
Digital cameras
PCMCIA
Digital Hi-Fi
Robotics
CAN bus
Network computers
Video phones
Graphics acceleration
Badge readers
Fax machines
DVD
Music synthesizers
Cable modems
Hubs
IIC
Optical drives
Security systems
Security systems
PCI
Digital monitors
Color correction
Card bus
Arcade games
Modems
VCR
Hard drives
Process controllers
USB
Audio
LANs
Video editing
Consumer electronics
Internet appliances
DSP
Click drives
Printers
Medical imaging
Digital VHS
Video capture cards
MPEG/JPEG
Video conferencing
Satellite base stations
Camcorders
Handheld scanners
Test equipment
POS terminals
Voice processing
Multimedia
Personal digital assistants
CDROM drives
GPS
Video conferencing
Digital audio mixing desks
Bar code readers
Reconfigurable computing
Telephony
Digitizers
PCS ground stations
Automotive cabin controls
Fiber optics
PBX switches
Copiers
PC network cards
Imaging systems
64
High-Volume FPGA Price Leadership
20 10

• New Applications
• Set Top Box
• DVD
• Digital Camera
• PC Peripherals
• Consumer Electronics

200k
100k
60k
Density (System Gates)
100k
60k
25k
40k
10K Gates Per Dollar in 2002!
15k
1997
1998
1999
2000
2001
2002
100k unit volume price projections
65
CPLD Price Leadership

• No Compromises
• Flexible ISP
• tPD 4ns (99) 2.5ns (02)
• Best Pin-Locking
• Industry Standard JTAG
• 2.5V (0.25m Flash) in 1999

Prices are based on 100ku, slowest speed
grade, lowest cost package
66
Solutions for Low-Cost, High-Volume
Applications

• Low cost programmable logic
• SpartanXL FPGAs available
• XC9500XL CPLDs available
• High performance
• System-level features
• Ease of evaluation and design
• WebFITTER, Foundation 1.5i software available