EE573 VLSI ?????

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EE573 VLSI ?????

• 2004 ?? ? ??
• ? ??

2
?? ??

• ?? ??? ?? (??? ??, know-what ? ??? ?? ???, ????
  ???? ??? ? ??) SoC ???? ??? ?.
• ?? LG MM-gt ????? 201 ?(?)
• ?? ???, ???
• Website QA(??, ??), ?? ? ?? ???, ??? ?? ????
  ?? ?? ??(1? ??)(http//vswww.kaist.ac.kr/course/e
  e573/)
• Text ?? ??
• Reference ?? ??

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EE573 ?? ??? ??

• (1 3/3) IT Future Trend and Role of SoC VLSI
• (1 3/8) Various SoC-Related Applications,
  Business Models, Global Industries Career/Life
  Planning
• (3 3/10,15,17) Key Issues in Embedded System
  Design
• (Requirement Generation HW/SW Co-Design and
  Co-Verification)
• (3 3/22,24,29) High-Speed Design Techniques
• (0.5 3/31) 45-min.Test(Mid-term)
• (1.5 3/31,4/7) Signal Integrity Issues
• (3 4/12,14,19) Infrastructures (Power/Ground
  Clocks), Interconnections and Packaging
  Techniques
• (1 4/21) IP-Based Design Methodology
• (1 4/26) How to present, write, talk, discuss,
  negotiate and live successful life
• (1 4/28) Testing, Reliability and Manufacturing
  Issues
• (1 5/3) Reconfigurable Systems Design Techniques
• (1 5/10, 730 am-1030 am) Poster Presentation
• (2.5 5/11,17,19) Low-Power Design Techniques
• (0.5 5/19) 45-min Test (Final Exam)
• (2 5/24, 6/2) Memory System Design Techniques
• (2 6/14, 6/16, 730 am-1030 am) Oral
  Presentation (15 min. for each person)
• Total 27 units

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?? ??? ??

• (No. of units Date) Subject of Learning
• (1 3/3) IT Future Trend and Role of SoC VLSI
• (1 3/8) Various SoC-Related Applications,
  Business Models, Global Industries Career/Life
  Planning
• (3 3/10,15,17) Key Issues in Embedded System
  Design
• (Requirement Generation HW/SW Co-Design and
  Co-Verification)
• (3 3/22,24,29) High-Speed Design Techniques
• (0.5 3/31) 45-min.Test(Mid-term)
• (1.5 3/31,4/7) Signal Integrity Issues
• (3 4/12,14,19) Infrastructures (Power/Ground
  Clocks), Interconnections and Packaging
  Techniques
• (1 4/21) IP-Based Design Methodology

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?? ??? ??

• (1 4/26) How to present, write, talk, discuss,
  negotiate and live successful life
• (1 4/28) Testing, Reliability and Manufacturing
  Issues
• (1 5/3) Reconfigurable Systems Design Techniques
• (1 5/10, 730 am-1030 am) Poster Presentation
• (2.5 5/11,17,19) Low-Power Design Techniques
• (0.5 5/19) 45-min Test (Final Exam)
• (2 5/24, 6/2) Memory System Design Techniques
• (2 6/14, 6/16, 730 am-1030 am) Oral
  Presentation (15 min. for each person)
• Total 27 units

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Grading System

• Homework 5 pieces (20)
• ?? n ?? ??? (n-2) ? ??
• Midterm 15
• Final 15
• Poster(10) Presentation(10) 20
• Oral Presentation(15) Written Paper (15)
  30

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IT Future Trend and Role of SoC VLSI

• 3/3 (1)

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What is SoC??

• Printed Circuit Board vs. Silicon board
• Design Reuse ? Use IP !!
• Design Specification ? Use C Language !!
• Verification Methodology ? In-System Verification
  !!

RTL
?P
Netlist
ROM
vs.
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Advent of SOC

• Growing design productivity gap between gate
  density (58/Y) and designer productivity (21/Y)
• Shrinking Time-To-Market (narrow market window)
• Viable solution ? Design Reuse

International Technology Roadmap For
Semiconductors 1999 Ed. - Semiconductor Industry
Association
Wireless Communications Report, BIS, Boston,
1995 Dataquest
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Evolution of reuse
Until early 80s TTL/MSI Reuse of Tr.
80s-90s ASIC/ASSP Reuse of Gates
Late 90s System-on-chip Reuse of Socketized IP
Hard component from A company
Virtual component from C company
Hard component from B company
Virtual component from D company
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Design methodology reuse model
Plug play SOC
Complex ASIC with a few IPs
ASIC on DSM
Logic
Platform-based design (PBD)
Block-based design (BBD)
Timing-driven design (TDD)
Area Driven
Personal Reuse Designer-specific reuse
practices Retaining key personnel
Source Reuse Functional starting points for
block design Document, testbench, predictability
Core Reuse Predictable, Pre-verified, Core
function Firm/hard IP
Virtual Component Reuse Socketized Functions
for Plug Play integration
Planned IP Reuse
Opportunistic IP Reuse
Adopted from Surviving the SOC revolution by H.
Chang et.al.
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Mote
13
Artist's conception of future MFI with optical
flow sensors and radio. (Quan Gan, UC Berkeley,
March 2004)
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• Homework 1 (Smart Dust by Pister) Read the
  following thesis and comment. (due 2 weeks 3/17
  class)
• http//www-bsac.eecs.berkeley.edu/archive/users/ho
  llar-seth/publications/cotsdust.pdf

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Composition of TWG (2003)
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(No Transcript)
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Future Prospect of IC Technology (ITRS)

• 2002. 9.9

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Contents

• Introduction
• ITRS
• Overall Roadmap
• Product Generation
• Lithography
• Package
• Power
• Cost
• Design Technology Challenges
• Introduction
• Complexity, Methodology
• Design Technology Challenges

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ITRS Introduction

• ITRS
• International Technology Roadmap for
  Semiconductors
• Predicts the main trends in the semiconductor
  industry
• Provides a reference of requirements, potential
  solutions, and their timing for the semiconductor
  industry
• ITWG (International Technology Working Group)
• http//public.itrs.net

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ITWG

• Overall Cordination
• ORTC(Overall Roadmap Technology Characteristic)
• System Driver
• Focus ITWGs
• Design
• Test
• Process Integration, Device, and Structures
• Front End Process
• Lithography
• Interconnection
• Factory Integration
• Assembly and Packaging
• Crosscut ITWGs
• Environment, Safety, and health
• Yield Enhancement
• Metrology
• Modeling and Simulation

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Prediction Classification

• Red Brick Wall
• There are no known manufacturable solution to
  continued scaling
• Historical trends of progress might end if some
  real breakthroughs are not achieved in the future
• Yellow defined as manufacturable solutions are
  known
• White defined as manufacturable solution are
  known and are being optimized

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ITRS2001

• ITRS(2001)
• Reports Improvement Trends
• Integration Level (Moores Law), Cost, Speed,
  Power, Compactness, Functionality
• Provides 15-years outlook on the major trends
• Each technology written by corresponding ITWG
• (International Technology Working Group)

Composition of the ITWG
lt By Regions gt
lt By Affiliations gt
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ITRS2001
lt Production Ramp-up Model and Technology Node gt

• Production time (year of production)
• When the first company brings a technology to
  production and a second company follows within
  three months

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Product Generation

• Product Generations Chip-Size Model
• DRAM
• (Historically recognized as the technology
  drivers for the entire semiconductor industry)
• Minimization of the area occupied by the memory
  cell
• ??Maximization of the capacitance for charge
  storage
• MPU/ASIC
• Length of the transistor gate
• Number of interconnect layers
• Metal half-pitch will trail slightly behind or
  equal to the DRAM half-pitch
• DRAM and microprocessor products will share the
  technology leadership role

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Product Generation

• Product Generations Chip-Size Model

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Product Generation

• Product Generations Chip-Size Model

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Lithography

• To maintain historical trend
• (Reducing cost/function by 2530/year)
• Enhance equipment productivity
• Increase manufacturing yields
• Use the largest wafer size available
• Increase the number of chips available on a wafer

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Package

• Number of Pads and Pins
• Increase number of I/O signals
• For higher number of functions on a single chip
• Additional power and ground connections
• To optimize power management
• To increase noise immunity
• MPU (12 I/O power/ground)
• Two power/ground pads for every signal I/O pad
• ASIC (11)
• One power/ground pad for every signal I/O pad

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Package

• Number of Pads and Pins

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Package

• Pin count/Cost-per-pin
• of package pin/balls increases at 10/year
• Cost/pin decreases at 5/year
• Average cost of packaging will increase at
  5/years
• To reduce the overall system pin requirements
• Combining functionality into SOC
• Multi-chip modules
• Bumped chip-on-board

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Package

• Pin count/Cost-per-pin

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Package

• Electrical Signals
• Instructions/second doubles every 1.52 years
• Increase Processing power
• To optimize signal and power distribution
• Increasing of layers of interconnect
• Size downscaling of interconnect
• Using copper(low resistivity)
• Using inter-metal insulating materials of lower
  dielectric constant

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Power

• Reduction of power supply voltage
• Reduction of power dissipation
• Reduction of transistor channel length
• Reduction of reliability of gate dielectrics

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Cost

• Reducing cost per function by 2530/year
• Twice the functionality on-chip every 1.52 years

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DT Introduction

• DT
• Enables the conception, implementation, and
  validation of microelectronics-based systems.
• Include tools, libraries, manufacturing process
  characterization, and methodologies
• Area
• Design Process
• System-Level Design
• Logical/Circuit/Physical Design
• Design Verification
• Design Test
• Crosscutting Challenges
• Productivity
• Power
• Manufacturing Integration
• Interference
• Error-Tolerance

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Design Productivity Gap

• of available transistors grows faster than the
  ability to design them meaningfully
• Investment in process technology has by far
  dominated investment in design technology
• Software now routinely accounts for 80 of
  embedded systems development cost
• Verification engineers are twice as numerous as
  design engineers on microprocessor project team
• Test cost has grown exponentially relative to
  manufacturing cost

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Design Productivity Gap
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DT Complexity

• Silicon Complexity
• Non-ideal scaling of device parasitics and
  supply/threshold voltages
• Leakage, power management, circuit/device
  innovation, current delivery
• Coupled high-frequency device and interconnect
• Noise/interference, signal integrity analysis and
  management, substrate coupling, delay variation
  due to cross-coupling
• Manufacturing equipment
• Statistical process modeling, library
  characterization
• Scaling of global interconnect performance
  relative to device performance
• Communication, synchronization

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DT Complexity

• 5. Decreased reliability
• Gate insulator tunneling and breakdown integrity,
  joule heating and electromigration, single-event
  upset, general fault-tolerance
• 6. Complexity of manufacturing handoff
• Reticle enhancement and mask writing/inspection
  flow, NRE cost
• 7. Process variability
• Library characterization, analog and digital
  circuit performance, error-tolerant design,
  layout, reuse, reliable and predictable
  implementation platforms

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DT Complexity

• System Complexity
• Reuse
• Support for hierarchical design, heterogeneous
  SOC integration (modeling, simulation,
  verification, test of component blocks)
  especially for analog/mixed-signal
• Verification and test
• Specification capture, design for verifiability,
  verification reuse for heterogeneous SOC,
  system-level and software verification,
  verification of analog/mixed-signal and novel
  devices, self-test, intelligent noise/delay fault
  testing, tester timing limits, test reuse
• Cost-driven design optimization
• Manufacturing cost modeling and analysis, quality
  metrics, co-optimization at die-package-system
  levels, optimization with respect to multiple
  system objectives such as fault tolerance,
  testability, etc.

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DT Complexity

• 4. Embedded software design
• Predictable platform-based system design
  methodologies, co-design with hardware and for
  networked system environments, software
  verification/analysis
• 5. Reliable implementation platform
• Predictable chip implementation into multiple
  circuit fabrics, higher-level handoff to
  implementation
• 6. Design process management
• Design team size and geographic distribution,
  data management, collaborative design support,
  design through system supply chain management,
  metrics and continuous process improvement

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DT Methodology Precepts

• Design Methodology combines
• Top-down planning and search (system
  specification and constraints) with
• Bottom-up propagation (physical laws, limits of
  manufacturing technology/cost)

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DT Methodology Precepts

• Future Design Methodologies and component tools
• Exploit reuse
• Evolve rapidly( evolution of suite vectors from
  simulation to verification, constraints for
  synthesis and optimization, and test)
• Avoid iteration
• Replace verification by prevention(ex
  lower-level problems, i.e., crosstalk/delay
  uncertainty, can be better addressed by
  upper-level prevention, i.e., shielding/repeater
  insertion)

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DT Methodology Precepts

• Improve predictability
• Orthogonalize concerns divide and conquer, treat
  separately
• if possible(computing and communication,
  behavior and architecture, etc.)
• Expand scope gather and conquer, treat together
  if possible(digital and analog, digital HW and
  software, internal,, operation and human
  interface, multi-level modelling, simulation)
• Unify synthesis and analysis, logical/physical/ti
  ming, design and test.

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DT Methodology

• Methodology Precepts

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Design Technology

• DT Area
• Design Process
• System-Level Design
• Logical, Circuit, and Physical Design
• Design Verification
• Design Test

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Design Technology
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ITRS 2003 Roadmap(1)
year 2004 07 10 13 2016
DRAM ½ pitch nm 90 65 45 32 22
MPU gate length nm (printed/physical) 53/37 35/25 25/18 18/13 13/9
Vdd V (high-perf./low power) 1.2/0.9 1.1/0.8 1.0/0.7 0.9/0.6 0.8/0.5
Max. power consumption W (hi-perf./cost-perf./battery) 158/84/ 2.2 189/104/ 2.5 218/120/ 2.8 251/138/ 3.0 288/158/ 3.0
MPU/ASIC metal 1 ½ pitch DRAM ½ pitch?
1.2 Si atom size ? 0.5 nm
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ITRS 2003 Roadmap(2)
Year 04 07 10 13 16
MPU chip size mm2 (intro./prod.) 280/ 140 280/ 140 280/ 140 280/ 140 280/ 140
ASIC max. chip size mm2 572 572 572 572 572
Litho. Field size mm (L/W) 32/22 32/22 32/22 32/22 32/22
Wafer diameter mm 300 300 300 450 450
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ITRS 2003 Roadmap(3)
Year 04 07 10 13 16
Total of pads (MPU) 3072 3072 3840 4224 4416
Total of pads (ASIC) 3600 4400 4800 5400 6000
Pad pitch um (ball/wedgy) 35/25 25/20 20/20 20/20 20/20
Pad pitch um (area flipchip/periphral fc) 150/60 120/30 100/20 90/20 80/15
? for signal I/O, ? for PWR/GND ½ for
signal I/O, ½ for PWR/GND
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ITRS 2003 Roadmap(4)
Year 04 07 10 13 16
Clock frequency MHz (on-chip clock/chip-to-board) 4171/ 2500 9285/ 4883 15079/ 9536 22980/ 18626 39683/ 36379
Max. of wiring levels (Max./Min.) 14/10 15/11 16/12 16/12 18/14
of mask levels (MPU/DRAM) 31/24 33/24 35/26 35/26 39/26
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Near-term Breakthroughs in Design Technology for
AMS
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(IT/SoC)IT? ??? ??
??(Information)/??(Knowledge)? ??, ??

• Last frontier after mass, wave and energy !

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IT? 3(1)? ?? (?????software)wireless ????

• ??? ??? ?? ??? ??

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IT??? ??,??,??,??? ?? methodology

• Medium(???, fiber, free space, molecule),
  mechanism(motor, ?????, )? information
  carrier(??, photon, E/M wave, )? ???? ???.

?)
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7) IT ???? overview

• ??? ??/??
• HW ?? sensor(??, ??, ??)
• System ???/TV ???, ?? satellite, ????, ????
• ??? ??
• HW ?? transducer, A/D-D/A ???, rf ???,
  serdes, codec
• SW compiler, assembler, ??? ??

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• ??? ??
• HW software platform(microprocessor,
  microcontroller, DSP), FPGA, ASIC, PC, Computing
  Server
• SW cryptography, authentication, ??/?? ??? ? ??
  CDMA, ?? ?? ? ???, ?? ?? ? ??, motion
  estimation, e-commerce, RTOS, ??/?? ??, EDA
  tools, 3-D graphics, animation, spreadsheet
• System PC, NMR, ??????, PDA, GPS, cellular phone

61

• ??? ??
• HW HDD, CD, CD-ROM, MOD, DVD, SDRAM, DRAM,
  FRAM, MRAM, Flash, tape
• SW ????? ???, DBMS
• System RAID, Smart card

62

• ??? ??
• HW fiber optics, switch, laser diode, antenna,
  IrDA
• SW TCP/IP, MPLS, ATM/ethernet protocol,
• MAC protocol, IPv6, TP monitor
• System router, repeater, NIC, homePNA,
  bluetooth
• ??? ??
• HW ????, LCD, PDP, EL display, speaker,
• printer head
• System micro-robot, TV, laser/ink-jet printer,
  motor,
• CNC machine

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IT vs. ???/????
?? ???? ?? ?? ?? ?? ?? ?? ?? (warfare) ??/ ?? (CT) ?? ?? (ET)
IT ? ? ? ? ? ?
BT ? ? ? ?
NT ? ? ? ? ? ?
???? ? ? ? ? ? ?
????? ? ? ? ?
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??? IT ??/????

• ??
• ?? IT ????? ???
• IBM, Intel, Lucent, HP, Motorola, TI, SUN, Cisco,
  SGI, Broadcom ? ???, hardware ? system ??,
  Microsoft, Oracle ? software ??, Yahoo, Netscape
  ? internet ?? ? ?? ??? ?? ??
• Stanford, MIT, Berkeley ? ????? ???? ??? ???? ??

65

• ???? Roadmap, ?? Standard, Consortium ??? ??? ???
  ??? ??
• ??? ??? MA? ?? ??/??
• Software? System ?? ????, ?? standard ???
  royalty? ?? ?? ??? ?
• BT? NT ??? ???? ??? ??? ??? ???

66

• ???, software, ??? ?? ? ?? ? ??? ??? ?? IT ???
  ??? ??? 1970???? ?? ??? ????? ??? ??? ??? ???
  1990??? ????? ???? ?
• ???? ????, MD ? ????? IT ??? booster ?? ? ???
  ???? ?
• ??, ??, ??, ??? ?? ?? ??? ??? ??

67

• ??
• ????, ??????, ????? ??? ??? ?? ??
• ???, ???? ?????? ?????, ??? ?? ? ????? ??? 10???
  ?????, PC? ?? ?? ???? ???? ??? ?

68

• ??? ??? ???? ??(?? ???? ???, ?? ???? ?? ??)? ??
  ??? ????? ???? inter-operability? ???? ??????
  ??? ?? ???? ???. ??? ?? ??? ???, ??? ????? ??.
• ??? ?? ????? ???? ???? ? 10?? ??? ? ?? ??? ?????
  ???? ?? ??

69

• ??
• Infineon, Mercedes, BMW, Bosch, AEG, Siemens ?
  ??? ??? Fraunhofer, Max Planck ??? ? ??
• ???? ?? ?? ??
• ??, ???, ??, ??? ?? ?????? ??? ??

70

• ??
• ????? ??? IT ?? ????
• ARM?? microprocessor core ??? ??? ?? ??
• software, marketing, ??, financing ??? ??
• ???
• 1984? ??? IMEC? ??? ?? ?? ? 100M ??? ????, ???
  ??? ??, ?????

71

• ????
• ?????? Technion(???? ?? ????? 70 ??), ?????
  Weizmann Institute? ????.
• ?? Nasdaq ????? 77?(???? ?? ??? ? ??? 120??)? 2??
  ???(126?)? ?? 3?
• ???? ????(Intel, IBM, Motorola ?)? ???? ??
  Technion ??? ?? ??? ??? ??.(??, Intel? ??
  processor? ????? software ??? ?????? ?.)

72

• ??? ?? ?? 10,000?? 135??? 2?? ??(85?)?? ?? ??
• ?????, ????, ????, ?? ? ????? ???
• BT? ??? ?? ?? ??(Weizmann? ?? ?? ??, ???? ????
  35? BT ??, ? ???? 40? BT? ??)

73

• ??
• 1973??? ??? ITRI(Industrial Technology Research
  Institute ???????)? ????? ????? ??? ??
• ERSO(Electronics Research Service
  Organization)? ??? ?????? UMC, TSMC? ?? ? ??? ???
  ???

74

• ??? ??? HSIP(Hsinchu Science-based Industrial
  Park)? 1980?? ???? ?? 3? ???? ??? ?? ??? ????
  ???, ???? ??? ???? ??????? ???? ?? ??. ?????
  ????? ???????? ????, ???? ?????? ??? ?? ????.

75

• ???
• ?????? 20? ??? Wireless Valley? KISTA Science
  Park 700?? ???? ??(Ericsson, IBM, ??, ?, ??,
  HP, Nortel ?)? 140? ??? 3?? ???? ?? ??
• Wireless Valley? Silicon Valley? ?? ? 2? ??? ???
  ???? ???? ??? ????? ??, ?????? ?? ??? ???(????
  ???? W-CDMA, Bluetooth, Optical Switching, DNA
  computing ?)

76

• Ericsson ???? ?? ?? ??? 40? 1?
• Sweden? ?? ???? ?? GDP ?? ???? ??(GDP? 3.8)
• ?? ????? ???????? ???? ??? 1?(7.72), ??
  2?(7.29), ?? 3?, ??? 4?
• KISTA ??? ??? RIT(??????)? IT campus? ???? ???
  ???? ??. ? ??? ????

77
SoC comes from(needed expertise)