More Quality

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More Quality

• Anselmo Lastra

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Topics

• SAGE (SIGGRAPH 2002)
• WarpEngine (SIGGRAPH 2000)

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SAGE (2002)

• Deering and Nagle, Sun
• 80M tris/sec, sort-last
• High-quality antialiasing a key feature
• Topics
• Motivation (market issues)
• Architecture
• Antialiasing
• Note There was a SAGE architecture (from IBM
  research) presented at S88

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Motivation

• Say display resolution grows lt 10/yr
• Antialising will increase the effective
  resolution of current display devices
• Out of reach of single-chip systems
• Pin-count X pin-data-rate bandwidth-per-chip
  lags well below Moores rate
• Say that while demand for triangle rate is
  increasing, decrease in size of tris making
  fill-rate demand grow more slowly

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Block Diagram
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Command Distribution

• Master chip
• DMA to/from host
• Contains MMU
• So graphics data can be in virtual mem
• Primitives distributed to 4 units
• Load balanced

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Geometry

• MAJC
• Microprocessor Architecture for Java Computing
• Meant for media processing
• 2 VLIW CPUs/chip
• 4 Functional-Units/Processor

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Rasterizer

• Programmable non-uniform sample locations
• 8-16x extra fill
• 256MB texture mem
• Replicated for polygon rend (not for volrend)
• Nothing said about programmable shading
• 2 output buses

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3DRAM or FBRAM

• Deering, S94
• Render pins write only (no R/W)
• Z buffering on chip
• Multiple chips communicate to agree on z value,
  and z-color write
• Blending ops for color
• Video out pins

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Sched Chips

• Sort-Last
• Sample buffer interleaved
• Chips interleaved by sub-samples
• Green circles are programmable switches
• Allow data to flow from a single input for a time
  to ensure cache coherence
• Fixed of samples
• So list is implicit
• Table in Rasterizer Convolve chips
• Tokens used to enforce ordering

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Route

• Scans out subsamples
• 640 pins
• 20 per 3DRAM
• 10 Route chips as 2-bit slices
• 40 bits/sample

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Convolve

• Each supports vertical swath of screen
• Computes 5x5 filter
• Overlaps neighbors by 2 pixels
• Aggregate data rate 8GB/s

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Convolve (2)

• Buffers 6 swaths
• 64 sample locations
• 6-bit offsets
• 2D hash to permute access
• Sample location table kept on chip
• May be different than one in Rasterizers because
  those chips are working on next frame
• Sample locations can change per frame
• Filter coefficients computed dynamically
• Filters programmable but must be radially
  symmetric

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Subsamples

• 16 samples/pixel
• Faint red lines are pixels
• 11 triangles
• Green lines

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Example
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Closeup
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Reference

• Michael F. Deering, Stephen A. Schlapp, Michael
  G. Lavelle, FBRAM a new form of memory optimized
  for 3D graphics, SIGGRAPH94

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WarpEngine

• Hardware architecture for rendering from depth
  images
• We didnt built it
• Voicu Popescus PhD
• Popescu, Voicu, John Eyles, Anselmo Lastra, Josh
  Steinhurst, Nick England and Lars Nyland, "The
  WarpEngine An Architecture for the
  Post-Polygonal Age, Proceedings of SIGGRAPH
  2000, New Orleans, July 2000, 433-442

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Rendering Algorithm

• WarpEngine algorithm
• Interpolate between reference image samples
• Warp (transform) them forward to image space
• Z-composite into sub-pixel (2x2) warp buffer
• No interpolation
• across skins

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Forward vs. Backward Map

• Conventional scan conversion
• For each pixel, compute color
• Basically backward map
• WarpEngine
• Warp sample forward

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Offsets Make it Work

• 2-bit offset
• More precise sample location
• 2-pixel wide filter kernel
• Similar to sparse buffer

Blue pixel, Green warp buffer, Black - offset
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Inexpensive Antialiasing
2 x 2 Offset
No Offset
Zoomed
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Why Forward Map?

• Low setup cost!
• No edge-expression computation
• Exploits coherence
• IBR tile (16x16 image) tends to need same
  interpolation factor
• Can use efficient SIMD warper

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Architecture
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WarpArray

• Nearest neighbor connectivity
• In/Out/Warp pipelined
• Similar to PixelFlow design

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Region Accumulator

• Pixel interleaved
• 128 x 128
• Soft z?
• Reconstruction pipelined with next region
  rendering

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Sort First for Parallelism

• How to distribute work across chips?
• Sort by screen space regions
• 128x128 pixel region
• Sort First Mueller refers to sorting primitives
  as soon as possible
• Tile coherence lowers overlap factor

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Expected Chip Specs (2000)

• ASIC 12x16 mm
• 0.18 micron
• ? 300 MHz
• 4-node VGA
• 32-node HDTV
• Each chip
• 100M Samples/sec
• 4.8G Bytes/sec bandwidth

Simulation on video
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WarpEngine References

• Voicu Popescu, John Eyles, Anselmo Lastra, Josh
  Steinhurst, Nick England and Lars Nyland,
  WarpEngine An Architecture for the
  Post-Polygonal Age, Proceedings of SIGGRAPH 2000,
  New Orleans, July 2000, 433-442
• Voicu Popescu, Anselmo Lastra, John Eyles,
  Sort-First Parallelism for Image-Based Rendering,
  Proceedings of Eurographics Workshop on Parallel
  Graphics and Visualization, Girona, Spain,
  September 2000.
• Popescu, Voicu, Anselmo Lastra, The Vacuum
  Buffer, Proceedings of the 2001 ACM Symposium on
  Interactive 3D Graphics, Research Triangle Park,
  NC, March 19-21, 2001, 73-76.