AVR Serial Communication

1
AVR Serial Communication

• Assembly Language Programming
• University of Akron
• Dr. Tim Margush

2
USART

• Universal Synchronous and Asynchronous serial
  Receiver and Transmitter
• A standard I/O device that provides conversions
  between serial and parallel data
• Provides a basic protocol for serial
  communication
• Speed, framing, error control

3
RS232

• This is a standard specification for the physical
  layer of a serial data interchange
• Specifies physical connections and voltage levels
• Data is transferred as a series of bits
  represented by voltage levels varying over time
• The encoding of data and signal interpretation is
  left to software

4
RS232 Basics

• For asynchronous communication, only three lines
  are needed
• Common ground
• Transmitted data (TD)
• Received data (RD)
• Note that the transmit line on one end is the
  receive line on the other end
• Other lines are used for various signaling options

Gnd
Gnd
RD
RD
TD
TD
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General Asynchronous Serial Communication

• The transmit line idle signal is 1 (mark)
• The transmitter signals the start of a frame by
  asserting a 0 (space) on TD
• At regular intervals (the baud rate), the
  transmitter asserts the bits of data, least
  significant first
• One or two stop bits (1) terminate the frame
  ending

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AVR USART

• UART or USART is a standard I/O device
• The ATMega16 has a USART integrated on-chip,
  producing logic signals for RS232 communication
• The microcontroller will only produce /- Vcc,
  which is typically 5V RS232 specifies /-12V
• The STK-500 includes a level converter between
  the serial connector and the microcontroller pins

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USART Components

• Transmitter
• Manages stream of bits for each byte
• Receiver
• Manages receipt of bits and assembly into byte
• Clock Generator
• Allows the USART to operate in synchronous or
  asynchronous modes

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Physical Connections

• The USART utilizes two external pins on the
  microcontroller for transmit and receive
• TxD is PD1
• RxD is PD0
• These bits of PORTD cannot be utilized for
  general digital I/O while serial communication is
  taking place

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AVR USART

• Note the three control and Status registers and
  external pins

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Clock Generator Section
Logic circuit to create correct clock signal for
receive and transmit
Baud rate specified by a parameter in UBRR
An external clock signal is used for synchronous
communication the master device asserts signals
on XCK, the slave listens
Serial clock signal
11
Transmitter Section
Shift register shifts bits onto TxD pin
Place a byte in UDR to initiate transmit
A byte can be queued in UDR (Transmit) while
another byte is being transmitted
clock
12
Receiver Section
Shift register shifts in bits from RxD pin
Read byte from UDR when receiver indicates it is
ready
Up to two bytes can be queued until read from UDR
while the receive shifter can be processing a
third
clock
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Asynchronous Serial Communication Basics

• Data is transmitted in frames
• Each frame has a start bit, data bits, optional
  parity bit, and stop bits
• The transmit line is asserted high or low during
  successive time slices to transmit the bits of
  the frame
• The receiver watches the data, assembling the 0
  and 1 values detected in each time slice in a
  container of appropriate size
• Receiver and transmitter must use similar clocks

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Using the USART

• Setup the control registers for the desired mode
  of operation
• UCSRA USART Control and Status Register A
• Mostly status, however 2 bits control speed and
  mode
• UCSRB USART Control and Status Register B
• Mostly control bits, however 2 are data bits
• UCSRC USART Control and Status Register C
• All control related bits

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Preparation

• Set the baud rate
• Set the frame format
• Enable receive and/or transmit
• Transmit and receive operations can be interrupt
  driven, or polled

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Baud Rate

• .equ brp 103 Baud rate parameter
• ldi R17, high(brp)
• ldi R16, low(brp)
• out UBRRH, R17
• out UBRRL, R16

The baud rate parameter depends on the system
clock frequency and desired baud rate
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Baud Rate Parameter

• Consult a table or use this formula
• UBRR (baud rate parameter) is limited to 0 to
  4095
• fosc is the system clock frequency
• From table
• 2400 baud with 4 MHz clock, brp 103
• 9600 baud with 1MHz clock, brp 6

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Frame Format

• UCSRC
• bit 7 URSEL (register select (1UCSRC)
• bit 6 UMSEL (mode select) (0asynchronous)
• bits 54 UPM10 (parity mode)
• 00 disabled, 10 even, 11, odd
• bit 3 USBS (stop bits) (01 stop bit)
• bits 21 UCSZ10 (data size) (11 8 bit data)
• There is one more bit at UCSRB2 (UCSZ2) which is
  set to 1 for 9-bit data
• bit 0 UCPOL (clock polarity) (synch mode only)

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Frame Format

• Start bit begins frame
• 5 to 9 data bits follow
• Parity is inserted if so configured
• One stop bit is required to end the frame
• Next frame can start immediately after the stop
  bit(s) or the line can stay idle

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Typical Frame Setup

• Asynchronous, even parity, 2 stop bits
• ldi R16, 0b10101110
• out UCSRC, R16

not used
Required to write to UCSRC
11 8 data bits
2 stop bits
Asynchronous
10 even parity
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Enable Transmit and Receive

• Set the transmit and receive enable bits,
  clearing others
• ldi R16, (1ltltRXEN)(1ltltTXEN)
• out UCSRB, R16
• Or simply set the two enable bits, leaving
  everything else in the register unchanged
• sbi UCSRB, RXEN
• sbi UCSRB, TXEN

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Transmitting a Byte

• Transmission of a byte is initiated by writing it
  to UDR
• You must wait until the USART data register is
  empty, hence the loop
• sbis is skip if bit in I/O register is set

• Byte to send is
• in R16
• transmit
• wait for data
• register to
• be empty
• sbis UCSRA, UDRE
• rjmp transmit
• start transmit
• out UDR, R16

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Receiving a Byte

• Received bytes are buffered in a queue
• The USART has a 2 byte buffer
• The Receive Complete flag is set while a byte is
  pending in the buffer
• Reading UDR will clear the RXC when the buffer is
  emptied

• Copy received byte
• to R16
• receive
• wait for data
• sbis UCSRA, RXC
• rjmp receive
• get byte from
• buffer
• in R16, UDR

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UDR

• Writing to UDR stores a byte in the USART
  Transmit buffer and initiates transfer
• This also clears the UDRE flag
• Data Register is no longer Empty
• UDRE is set when the byte is moved into the
  transmit shift register by the USART
• Reading removes and returns the next byte from
  the USART receive buffer
• If the buffer is emptied, RXC is cleared

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Disabling Transmission

• Set TXEN to 0
• Bytes pending transmission will be sent before
  the transmitter is actually disabled
• TXC (Transmit Complete) is set when transmit
  buffer is empty and transmit shift register is
  empty
• When the transmitter is disabled, TxD pin resumes
  its normal PORTD function

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Disabling Reception

• Clear RXEN
• The receiver is immediately disabled and RxD
  functional is returned to PORTD
• All received data still in the buffer or in
  transit will be discarded

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Error Flags

• Located in UCSRA
• FE Frame Error
• 1 indicates the first stop bit was not found
• DOR Data OverRun error
• 1 indicates received byte could not be placed in
  the buffer and another byte reception was started
• PE Parity Error
• 1 indicates a parity error in received data
• Even parity expects an even number of 1's in
  data odd parity expects an odd number of 1's

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Reading Error Flags

• Errors are buffered with the received data
• Access errors before data
• in R17, UCSRA
• in R16, UDR
• You can then check bits in the register R17 for
  error indicators
• andi R17, (1ltltFE)(1ltltDOR)(1ltltPE)
• brne ReceiveError

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UCSRC and UBRRH

• These labels (I/O registers) are identical
• When writing to UBRRH, the most significant bit
  must be 0
• Since UBRR is at most 4095, this is automatic
• When writing to UCSRC, be sure to set bit 7
• ldi R16, (1ltltURSEL)other bit settings
• out UCSRC, R16

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UCSRC and UBRRH

• Reading these bytes is seldom necessary
• The first access returns UBRRH
• in R16, UBRRH
• If accessed in the next clock cycle, UCSRC is
  returned
• in R16, UBRRH
• in R16, UCSRC
• Note both of these instructions are the same
• UBRRH UCSRC 20
• in R16, 20