Title: Low Power Design in CMOS
1Low Power Design in CMOS
2Why worry about power?-- Heat Dissipation
microprocessor power dissipation
source arpa-esto
DEC 21164
3Evolution in Power Dissipation
4Why worry about power Portability
5Where Does Power Go in CMOS?
6Dynamic Power Consumption
7Dynamic Power Consumption - Revisited
8Power Consumption is Data Dependent
9Transition Probabilities for Basic Gates
10Transition Probability of 2-input NOR Gate
11Problem Reconvergent Fanout
12How about Dynamic Circuits?
134-input NAND Gate
14Transition Probabilities for Dynamic Gates
15Glitching in Static CMOS
16Example 1 Chain of NOR Gates
17Example 2 Adder Circuit
18How to Cope with Glitching?
19Short Circuit Currents
20Impact of rise/fall times on short-circuit
currents
21Short-circuit energy as a function of slope ratio
22Static Power Consumption
23Leakage
24Sub-Threshold in MOS
25Power Analysis in SPICE
26Design for Worst Case
27Reducing Vdd
28Lower Vdd Increases Delay
29Lowering the Threshold
30Transistor Sizing for Power Minimization
31Transistor Sizing for Fixed Throughput
32Reducing Effective Capacitance
33Summary