High Speed Low Current Comparator

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High Speed Low CurrentComparator

• Presented By
• GAURAV RAJA
• 2003EEN0013

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Overview

• Basic stages of current comparator
• Simple current comparator
• Proposed current comparator design
• Simulation results
• Conclusions
• References

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Basic stages of current comparator

• Current to voltage conversion
• Voltage amplification

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Simple current comparator
Current to voltage conversion
Voltage amplification
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Design specifications

• Slew Rate gt 70 V/us
• Load capacitor 1 pF
• Bias current 70 uA
• Input current switching between -100 nA to 100
  nA
• Reference current 0 A

Design is in such a way that it is not slew rate
limited
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Proposed current comparator
7.1u/1.2u
1u/.5u
0.7u/0.5u
All transistors are assumed to be in saturation
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Simulation Results of simple current comparator
Iin 100 nA
Delay time 8 ns
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Simulation Results of proposed current comparator
Iin 100 nA
Delay time 8 ns
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Plot of delay time as a function of input current
Simple CC
Proposed CC
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Simulation result for Vp0.5 V
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Proposed circuit
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Simulation result for Vn1.5 V
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Conclusions

• Delay time for 100 nA input current 12 ns
• Average power consumption 0.53 mW
• Delay time increases as the input current
  decreases.
• Proposed circuit can work with 21 ns delay, even
  with 10 nA.

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References

• Hongchin Lin, Jie-Hau Huang, A Simple High-Speed
  Low current comparator, IEEE ISCAS-2000,
  May,1994.
• P. Allen and D. Holberg, CMOS Analog Circuit
  Design, Oxford University Press, 2002.

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Thank You