LECTURE 1 DIGITAL ELECTRONICS

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LECTURE 1 DIGITAL ELECTRONICS
Dr Richard ReillyDept. of Electronic
Electrical EngineeringRoom 153, Engineering
Building
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Digital Electronic Market

• IC industry will grow 23 percent in 2004 over
  2003, but will then decline 8 percent in 2005.
  Gartner Research
• In 2005, the market will suffer from an excess
  capacity of 300-mm fabs in the industry.
• IC Insights projected that the worldwide
  semiconductor market would grow 15 percent in
  2003 over 2002. The firm recently revised its
  forecast, saying the market will reach 136.4
  billion in 2003 sales, a 13 percent growth rate
  over 2002.
• SIA projected worldwide semiconductor sales would
  increase 10.1 percent to 154.9 billion in 2003,
  16.8 percent to 180.9 billion in 2004, 5.8
  percent to 191.5 billion in 2005, and 7 percent
  to 204.9 billion in 2006.

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Digital Electronics

• Why is it so successful ?

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Digital Technology

• The success of digital technology is primarily
  based on simplicity of designing digital circuits
  and ease of their manufacture
• Digital circuits are composed of
• basic processing elements
• basic memory elements
•  
• Components are simply just gates and flip-flops.

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Digital Technology

• The simplicity of the design is inherent from two
  facts
•  
•   input or output signals of each gate/flip-flop
  can assume only two values
•  
•   Changes in the signal values are governed by
  laws of Boolean Algebra

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Digital Technology

• The fact that Boolean Algebra is finite and
  richer in properties than ordinary algebra leads
  to simple optimisation techniques for Boolean
  functions during their implementation with gates
  and flip-flops.
• Saw in previous courses (2nd and 3rd Year)
•  
• how to specify Boolean functions
• how to derive expressions for computing function
  values.

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How to implement Boolean expressions

• Construct logic networks or logic circuits
•  
• With variables in the expression as inputs to
  this logic network, which contains one or more
  logic gates.
•  
• Each logic gate performs one or more Boolean
  operations

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Digital Libraries

• The collection of logic gates that are used in
  the constructing logic networks is called the
  gate library.
• The gates in the library are called standard
  gates.
•  
•  
• Although every Boolean operator can be
  implemented as a logic gate and included in the
  gate library.
• modern gate libraries rarely include more than a
  dozen gates
• Gate Library lt10-15 entries
• to lower cost of library maintenance
• simplify the development of CAD tools for logic
  design.

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How do we select which operators are to be
included in the gate library?

• What criteria would you consider ?
•  

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How do we select which operators are to be
included in the gate library?

• Consider the following criteria
•  
• Frequency of use in typical logic design
• defined by its ability to implement a variety of
  Boolean functions in conjunction with other
  gates.
•  
• 2. Operator extensibility to more than two
  variables
• which requires its commutativity and
  associativity.
•  
• 3. Construction simplicity
• defined by the number of transistors needed for
  its construction and the time needed for the
  signal change to propagate through the gate.

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How do we select which operators are to be
included in the gate library?

• On the basis of these criteria, typically select
  only eight operators to be implemented as
  standard gates
•  
• Inverter (or Complement)
• Transfer
• AND
• OR
• NAND
• NOR
• XOR
• XNOR
•  
• The transfer operator is generally referred to as
  the Driver, since it is used for driving large
  loads and long connection lines.

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Basic Logic Library
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Digital Library

• The driver is equivalent to two inverters that
  are connected in cascade
• output of the first inverter serves as the input
  of the second.
• We have seen NAND and NOR are used to implement
  those functions which are complements of AND and
  OR.
• far more popular than the AND and OR gates
• simply because their implementation requires only
  four transistors
• Compare with AND and OR gates, which requires
  six transistors.
•  
• Due to requiring fewer transistors, the NAND and
  NOR gates are faster than the corresponding AND
  and OR gates

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Design Requirements

• When implementing Boolean functions with this
  basic gate library we are usually trying to find
  the Boolean expression that will best satisfy a
  given set of design requirements.
•  
•  

• What Design Requirements ?
•  
•  

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Design Requirements

• Generally design requirements involve
  restrictions.
• Cost can be given in terms of the number of
  transistors
• signal delay through the network, specified in
  nanoseconds

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As Digital Design Engineers we have two options

• Option 1
• Very frequently our main goal is to find the
  fastest design
• one with the smallest input/output delay
•  
•  Option 2
•  
• On the other hand our main goal will just as
  often be to find the least expensive design
• One with least number of gates.
•  

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Design Options

•  
• Both of these goals tend to be in conflict !!.
•  
• a faster design will usually evaluate common
  sub-expressions in parallel, will require more
  gates than a lower-cost design
• a lower-cost design all functions tend to be
  executed serially.

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Example Problem

• Design a full adder based on the specifications
  using the basic logic library to the following
  goals
• PRIMARY GOAL
•     minimise the propagation delay from Ci to
  Ci1
•  
• SECONDARY GOAL
•     use the smallest possible number of
  transistors.

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Solution

• 1st Part of Solution
•  
• Derive an expression with the minimum number of
  operators.
• The expression for can be reduced to two XOR
  gates.

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Solution

• 2nd Part of Solution
•  
• Investigate the expression for Ci
• We can convert it to a form, where we can use the
  sub-expression
• which is already part of the expression for Si
  

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Solution

• As both share common sub-expressions,
•  
• can implement the full-adder with five gates

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Solution

• Note this implementation
•  
• requires 46 transistors
• has a delay of 4.8 nsecs from Ci to Ci1

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• If we modify the expressions for Si to Ci1
• we can take full advantage of the faster, less
  expensive NAND and NOR gates.
• To do this we first transform the expression for
  Ci1
• using De Morgans theorems
• thus

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• Similarly, we transform the expression for Si
• In addition we can also implement
  with two NANDs and one OR gate

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Implementation

• Using these expressions, can implement the faster
  full adder shown below

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• Note this implementation of the adder
• Takes only 2.8 nsecs from Ci to Ci1
• in comparison to 4.8 nsecs for the previous
  design.
• Design would be less expensive, since uses only
  36 transistors
• instead of 46 required previously.

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Notes on Design

• NOTE 1
•  
• On the basis of this example, can generalise and
  say that
•  
• the attempt to minimise the number of operators
  will not necessarily yield
• the fastest
• even
• the least expensive design  
• but
•    
• if we try to find the expression that uses the
  fastest or least expensive gates in the library
• then we may achieve this goal.

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Notes on Design

• NOTE 2
•  
• Have only considered two-input gates
• the same principle can be extended to
  three/multi-input gates.

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Summary

• As digital design engineers we need for focus on
  the economics of the design and of the eventual
  manufacture
• Low Cost
• High Speed