LECTURE 7 DIGITAL ELECTRONICS

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LECTURE 7 DIGITAL ELECTRONICS
Dr Richard ReillyDept. of Electronic
Electrical EngineeringRoom 153, Engineering
Building
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MOS Transistors

• Smallest primitive logic element in TTL or ECL is
  the logic gate
•  
• Þ design may be accomplished while considering
  only the properties specified of each gates.
• although these gate properties may depend on
  internal circuit properties, the designer need
  not master details of circuit themselves.
•  
• For MOS technology devices may also be used to
  form gates.
• Þ can be treated as primitive elements
•  
• However it is possible to combine MOS devices
  into sub-networks that accomplish logic but not
  gates.

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MOS Transistors

• The field effect transistor (FET) is a unipolar
  transistor
• Operation depends on flow of only one type of
  carrier.
•    
• Two types of field-effect transistors
• Junction or J-FET
• used in linear circuits
•  
• Metal-Oxide-Semiconductor (MOS)
• used in digital circuits
• can be fabricated in less area than bipolar
  transistor

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Basic MOS structure

• P-channel MOS consists of
• a lightly doped substrate of n-type silicon.
• two regions heavily doped by diffusion with
  p-type impurities to form the Source and the
  Drain.
• Region between two p-type sections serves as a
  channel.

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Basic MOS structure

• Gate is metal plate separated from channel by an
  insulated dielectric of SiO2.
• Negative voltage (wrt substrate) at gate causes
  induced electric field in channel that attracts
  p-type carriers from substrate.
• As magnitude of voltage on gate increases
• region below gate accumulates more positive
  carriers.
• Conductivity increases
• current can flow from source to drain provided a
  voltage difference is maintained between two
  terminals.

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4 basic type of MOS structures.

• Channel can be p-type or n-type
• Mode of operation can be enhanced or depleted
• depends on the state of the channel region at
  zero gate voltage.
•  
• If channel is initially doped lightly with p-type
  minority carriers (diffused channel)
• a conducting channel exists at zero gate voltage
• device said to be operating in the depletion mode
• current flows unless the channel is depleted by
  an applied gate field

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P-Channel MOS

• Source connected to the Substrate
• Negative voltage applied to the Drain terminal
•  
• When Vgate gt VThreshold
• ? no current flows in the channel
• ? Drain to Source path is effectively an open
  circuit.
•  
• When Vgate lt VThreshold
• ? a channel formed
• ? p-type carriers flow from Source to Drain.
• p-type carriers are positive and correspond to a
  positive current flow from Source to Drain.

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N-Channel MOS

• Source connected to the Substrate
• Positive voltage applied to the Drain terminal.
•  
• When Vgate lt VThreshold
• no current flows in the channel
• When Vgate gt VThreshold
• ? a channel formed
• ? n-type carriers flow from Source to Drain.
• n-type carriers are negative and correspond to a
  positive current flow from Drain to Source.

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MOS Devices

• A very important property of MOS devices is that
  the gate draws no current.
• Regardless of the voltage at the gate
• It only controls the existence or non-existence
  of current between Source and Drain.

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N-channel Enhancement Mode Device
If VGS and VGD lt VTH ? switch is open ? no
current flows, ? IDS 0 ? device in Cut-off
 
If VGS gt VTH ? switch is closed ? current flows
Drain to Source  
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N-channel Enhancement Mode Device

• If Linear Region of Operation
• ?
•  
• for small values of VDS,
• ? is a constant, called the Gain Factor
• Beyond the linear region
• device is in saturation
• channel is said to be pinched-off

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N-channel Enhancement Mode Device

• From characteristics, linear and saturation
  regions for typical voltage values.
• Current in an NMOS transistor

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Layout of MOS devices

• The difference between linear and saturation
  regions is in the geometry of the inversion layer
  under the gate.
• influences amount of current that can pass
  through channel
•  
• In Digital Circuits
• Switch the transistors very rapidly between
  cut-off and saturation regions
• Without spending too much time in the linear
  region

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Gain Factor

• Layout of MOS devices on the chip is relevant to
  their logic design.
• Logic designers interest in layout will be
  confined to a 2-D map of devices on the available
  chip area.
• The gain factor ? is dependent on three
  parameters
• the geometry of the channel region and process
  parameters.
• Kp process gain factor. Is a constant for a
  given process technology
• W width of channel
• L length of channel

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Layout of MOS devices

• Structure of an NMOS transistor
• ? a critical parameter and can be controlled by
  the designer by varying the W/L ratio

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Current Drive Capability

• Therefore for a given process technology
• Designer can control the performance of a circuit
  by specifying W and L for each of the transistors
  utilised in the circuit.
• In general a large value for ? is preferred.
• ? improved drive capability
• ? W gtgt L

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Minimum Feature Length

• However, a limit to how short L can be made.
•  
• In general can regard the degree to which L can
  be made short as the limit of the process
  technology in terms of the resulting performance.
  
• Related to the commonly termed minimum feature
  length that can be delineated through
  photolithography.
• Currently 0.25micron (.25?m)
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• 3 other similar sites

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W gtgt L

• However associated disadvantages with W gtgt L
• More silicon area is used
• More power dissipated
•   
• Tradeoff
• Performance SiO2 Area Power

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Resistors

• When electrons flow in the channel
• they move length of the channel L
• Conduction in channel resembles conduction in any
  resistive area.
• Another advantage of MOS devices is that they can
  be used not only as a transistor but also as a
  resistor
• Resistor obtained by permanently biasing the Gate
  for conduction.
• Ratio of the Source-Drain voltage to channel
  current determines value of resistance.
• Different resistor values may be constructed
  during manufacturing by fixing L and W of the MOS
  device.

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Depletion Mode Operation

• Threshold voltage Vth can be reduced by
  implanting ions in the channel.
• When the Vth is reduced to 0.8 VDD
• ? results is called a depletion mode device
•  
• Threshold Voltage of depletion device referred to
  as Vdep
• Applications
• depletion mode device is preferred choice of the
  resistive load in an NMOS inverter.

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Depletion Mode Operation

• A variety of symbols exist for depletion mode
  devices

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P-Channel Enhancement Mode

• Structure of an PMOS transistor

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P-Channel Enhancement Mode

• Reversal in the structure of the previous
• ? n-type substrate
• ? p-type regions diffused
•  
•  
• Conduction takes place when charge on gate is
  sufficiently negative with respect to p-type
  source.
• ? channel formed by holes
•  
• The circle symbol denotes the p-channel device
• ? VGS must be less then some negative threshold
  value.

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PMOS

• Developed before NMOS
• Depended exclusively on p-channel devices
•  
• P-Channel devices are used primarily in
  conjunction with n-channel devices to from a
  technology known as Complementary MOS or CMOS

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Summary

• MOS devices provide a number of advantages for
  digital logic devices.
• MOS device architecture and operation provide a
  number of advantages to the digital designer to
  structure that architecture for different
  applications.